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PDF ICS950805 Data sheet ( Hoja de datos )
| Número de pieza | ICS950805 | |
| Descripción | Frequency Generator with 200MHz Differential CPU Clocks | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS950805
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK-408 clock for Almador-M and Brookdale-Mobile
chipsets. Programmable for group to group skew.
Pin Configuration
Output Features:
• 3 Differential CPU Clock Pairs (differential current
mode)
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 1 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
• 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
• 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
Features:
• Almador Chipset has a DLL driving the clock buffer
path for the 3 buffer path 66.6 MHz outputs,
66Buf(0:2). Almador board level designs MUST
use pin 22, 66Buf_1, as the feedback connection
from the clock buffer path to the Almador
(GMCH) chipset.
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
66MHz_OUT0/3V66_2
66MHz_OUT1/3V66_3
66MHz_OUT2/3V66_4
66MHz_IN/3V66_5
*PD#
VDDA
GND
Vtt_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 I REF
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
30 SCLK
29 SDATA
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
• Supports spread spectrum modulation,
* These inputs have 150K internal pull-up resistor to VDD.
down spread 0 to -0.5%.
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• 66MHz Output Jitter (Buffered Mode Only) <100ps
• CPU Output Skew <100ps
Block Diagram
Functionality
PLL2
48MHz_USB
FS2 FS1 FS0
CPU
(MHz)
3V66(1:0)
(MHz)
66MHzOut(2:0)
3V66(4:2)
(MHz)
PCI_F
PCI
(MHz)
66MHzIn
3V66(5)
(MHz)
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
PCI
DIVDER
Stop
3V66
DIVDER
48MHz_DOT
3V66_5/66MHz_IN
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0)
REF
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
PCICLK (6:0)
7
PCICLK_F (2:0)
3
66MHz_0
3V66_1/VCH_CLK
I REF
00
00
01
01
10
10
11
11
Mid 0
Mid 0
Mid 1
Mid 1
0 66.66
66.66
1 100.00 66.66
0 200.00 66.66
1 133.33 66.66
0 66.66
66.66
1 100.00 66.66
0 200.00 66.66
1 133.33 66.66
0 Tristate Tristate
1 TCLK/2 TCLK/4
0 Reserved Reserved
1 Reserved Reserved
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
Tristate
TCLK/4
Reserved
Reserved
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
Tristate
TCLK/8
Reserved
Reserved
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
Tristate
TCLK/4
Reserved
Reserved
0649H—02/25/05
1 page  
ICS950805
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
1
1
1
1
1
1
1
0
Type
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
5
6
7
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
Bit 3 5 PCICLK_F0
Bit 4 6 PCICLK_F1
Bit 5
Bit 6
Bit 7
7 PCICLK_F2
39 48MHz_USB
38 48MHz_DOT
PWD
1
1
1
0
0
0
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Allow control of PCICLK_F0 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
66MHz_OUT0/3V66-2
66MHz_OUT0/3V66-3
66MHz_OUT0/3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
PWD
1
1
1
1
1
1
0
0
Type
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
(Reserved)
0649H—02/25/05
5
5 Page 
ICS950805
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
Output Impedance
RDSP11 VO = VDD*(0.5)
Output High Voltage
VOH1 IOH = -1 mA
Output Low Voltage
VOL1
IOL = 1 mA
Output High Current
Output Low Current
Rise Time
IOH1
IOL1
tr11
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf11 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
Jitter
dt11
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
MHz
20 48 60 W
2.4 V
0.4 V
-29 -23 mA
29 27 mA
1 1.25 2
ns
1 1.15 2
ns
45 53 55 %
723 1000 ps
0649H—02/25/05
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ICS950805.PDF ] | |
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