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PDF ICS950810 Data sheet ( Hoja de datos )
| Número de pieza | ICS950810 | |
| Descripción | Frequency Generator with 200MHz Differential CPU Clocks | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS950810
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK-408 clock for BANIAS processor/ ODEM and
MONTARA-G chipsets.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Supports spread spectrum modulation,
down spread 0 to -0.5%. (CPU, 3V66, PCI)
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
VDDREF 1
X1 2
X2 3
GND 4
PCICLK_F0 5
PCICLK_F1 6
PCICLK_F2 7
VDDPCI 8
GND 9
PCICLK0 10
PCICLK1 11
PCICLK2 12
PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 IREF
41 GND
40 FS2
39 48MHz_USB
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK
34 PCI_STOP#*
33 3V66_0
32 VDD3V66
31 GND
30 SCLK
29 SDATA
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Functionality
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
PCI
DIVDER
Stop
3V66
DIVDER
48MHz_USB
48MHz_DOT
3V66_5
3V66_3
3V66_(4,2)
REF
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
PCICLK (6:0)
7
PCICLK_F (2:0)
3
3V66_0
3V66_1/VCH_CLK
I REF
FS2 FS1 FS0
CPU
(MHz)
X0
X0
X1
X1
Mid 0
Mid 0
Mid 1
Mid 1
0
1
0
1
0
1
0
1
166.66
100.00
200.00
133.33
Tristate
TCLK/2
Reserved
Reserved
3V66(5:0)
(MHz)
66.66
66.66
66.66
66.66
Tristate
TCLK/4
Reserved
Reserved
PCI_F
PCI
(MHz)
33.33
33.33
33.33
33.33
Tristate
TCLK/8
Reserved
Reserved
0472F—01/12/04
1 page  
ICS950810
Power Management
PD# CPU_STOP# PCI_STOP# VCO
CPU CPU# PCICLK
0X
X STOP Iref*2 FLOAT LOW
11
1
RUN
RUN
RUN
RUN
10
1 RUN Iref*2 FLOAT RUN
11
0 RUN RUN RUN LOW
11
1
RUN
RUN
RUN
RUN
Note: PCI_F is not affected by PCI_STOP# and CPU_STOP#
3v66
LOW
RUN
RUN
RUN
RUN
48MHz
LOW
RUN
RUN
RUN
RUN
REF
LOW
RUN
RUN
RUN
RUN
Tri-State Control of CPU Outputs
State
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Byte0 bit6
PD#
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Byte1bit6
Cpu_stop#
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Pin
PD#
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Pin
Cpu_Stop#
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Stoppable
CPU outputs
Running
Irefx6
Irefx2
Irefx2
Running
Hi-Z
Hi-Z
Hi-Z
Running
Irefx6
Hi-Z
Hi-Z
Running
Hi-Z
Hi-Z
Hi-Z
Free-Running
CPU outputs
Running
Running
Irefx2
Irefx2
Running
Running
Irefx2
Irefx2
Running
Running
Hi-Z
Hi-Z
Running
Running
Hi-Z
Hi-Z
0472F—01/12/04
5
5 Page 
ICS950810
I2C Tables
BYTE
Affected Pin
0 Pin #
Name
Bit 7
-
Spread Enabled
Bit 6
-
CPU_T(2:0)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
35 3V66_1/VCH_CLK
53 CPU_STOP#*
34 PCI_STOP#*
40 FS2
55 FS1
54 FS0
Control Function
Spread Spectrum Control
Power down mode output
level
0= CPU driven in power
down
1= undriven
VCH/66.66 Select
Reflects value of pin
Reflects value of pin at
power up. Also can be set.
Frequency Selection
Frequency Selection
Frequency Selection
Type
RW
RW
RW
R
R/RW
RW
RW
RW
Bit Control
01
OFF ON
HIGH LOW
66.66 48.00
Stop Active
Stop Active
--
--
--
PWD
0
0
0
X
1
X
X
X
BYTE
1
Bit 7
Affected Pin
Pin #
Name
43 MULTSEL0*
Bit 6
-
CPU_T(2:0)
Bit 5 45, 44
Bit 4 49, 48
Bit 3 52, 51
Bit 2 45, 44
Bit 1 49, 48
Bit 0 52, 51
CPUCLKT2
CPUCLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
CPUCLKT2
CPUCLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
Control Function
Reflects value of pin
Type
R
Bit Control
01
--
PWD
x
CPU_Stop mode output level
0= CPU driven when stopped RW
1 = undriven
HIGH
LOW
0
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
Output control
RW Not Freerun
Freerun
RW Not Freerun
Freerun
RW Not Freerun
Freerun
RW Disable Enable
0
0
0
1
Output control
RW Disable Enable 1
Output control
RW Disable Enable 1
0472F—01/12/04
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS950810.PDF ] | |
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