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Integrated Circuit Systems - Programmable Timing Control Hub for P4

Numéro de référence ICS950202
Description Programmable Timing Control Hub for P4
Fabricant Integrated Circuit Systems 
Logo Integrated Circuit Systems 





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ICS950202 fiche technique
Integrated
Circuit
Systems, Inc.
ICS950202
Programmable Timing Control HubTM for P4TM
Recommended Application:
CK-408 clock for Intel® 845 chipset.
Output Features:
• 3 - Pairs of differential CPU clocks @ 3.3V
• 3 - 3V66 @ 3.3V
• 9 - PCI @ 3.3V
• 2 - 48MHz @ 3.3V fixed
• 1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz
• 1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
VDDREF
X1
X2
GND
1**FS0/PCICLK7
1**FS1/PCICLK8
VDDPCI
GND
1*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF/FS2**1
47 CPUCLKT0
46 CPUCLKC0
45 VDDCPU
44 CPUCLKT1
43 CPUCLKC1
42 GND
41 VDDCPU
40 CPUCLKT2
39 CPUCLKC2
38 MULTISEL0*
37 I REF
36 GND
35 48MHz_USB/FS3**
34 48MHz_DOT
33 AVDD48
32 GND
31 3V66_0/VCH_CLK/FS4**
30 VDD3V66
29 GND
28 SCLK
27 SDATA
26 Vtt_PWRGD/PD#
25 GND
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
0461L—05/28/03
Frequency Table
FS4
FS3
FS2
FS1
FS0
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
0 0 0 0 1 100.00 66.67 33.33
1 0 0 0 1 133.33 66.67 33.33
1 1 1 1 0 66.67 66.67 33.34
1 1 1 1 1 200.00 66.67 33.33
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz

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