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PDF UPD23C64380 Data sheet ( Hoja de datos )
| Número de pieza | UPD23C64380 | |
| Descripción | (UPD23C64340 / UPD23C64380) 64M-BIT MASK-PROGRAMMABLE ROM | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD23C64340, 23C64380
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The µPD23C64340 and µPD23C64380 are 67,108,864 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The µPD23C64340 and µPD23C64380 are packed in 48-pin TAPE FBGA.
Features
• Pin compatible with NOR Flash Memory
• Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
• Page access mode
BYTE mode : 8 byte random page access (µPD23C64340)
16 byte random page access (µPD23C64380)
WORD mode : 4 word random page access (µPD23C64340)
8 word random page access (µPD23C64380)
• Operating supply voltage : VCC = 2.7 V to 3.6 V
Operating supply
voltage
VCC
3.0 V ± 0.3 V
3.3 V ± 0.3 V
Access time /
Page access time
ns (MAX.)
100 / 25
90 / 25
Power supply current
(Active mode)
mA (MAX.)
µPD23C64340
µPD23C64380
40 60
55 75
Standby current
(CMOS level input)
µA (MAX.)
30
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16335EJ3V1DS00 (3rd edition)
Date Published July 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2002
1 page  
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
µPD23C64340, 23C64380
O8 O9 O10 O11 O12 O13 O14 O15, A−1
O0 O1 O2 O3 O4 O5 O6 O7
Output Buffer
Y-Selector
WORD, /BYTE
/OE or OE or DC
Memory Cell Matrix
4,194,304 words by 16 bits /
8,388,608 words by 8 bits
/CE
Data Sheet M16335EJ3V1DS
5
5 Page 
µPD23C64340, 23C64380
Read Cycle Timing Chart 2 (Page Access Mode)
Upper addressNote 1
A2 to A21
(Input)
A3 to A21
tACC
/CE (Input)
tCE
/OE or OE (Input)
Page addressNote 1
A–1Note 2, A0, A1
(Input)
A–1Note 2, A0, A1, A2
O0 to O7,
(Output)
O8 to O15Note 4
tOE
tPAC Note 5
tPAC Note 5
tOH
tOH
High-Z
Data Out Data Out
tDF Note 3
tOH
Data Out
High-Z
Notes 1. The address differs depending on the product as follows.
Part Number
Upper address
Page address
µPD23C64340
A2 to A21
A–1, A0, A1
µPD23C64380
A3 to A21
A–1, A0, A1, A2
2. During WORD mode, A–1 is O15.
3. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
[ µPD23C64340 ]
Page access time
Upper address (A2 to A21)
inputs condition
/CE input condition
/OE or OE input condition
tPAC
Before tACC – tPAC
Before tCE – tPAC
Before stabilizing of page
address (A–1, A0, A1)
[ µPD23C64380 ]
Page access time
tPAC
Upper address (A3 to A21)
inputs condition
Before tACC – tPAC
/CE input condition
Before tCE – tPAC
/OE or OE input condition
Before stabilizing of page
address (A–1, A0, A1, A2)
Data Sheet M16335EJ3V1DS
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet UPD23C64380.PDF ] | |
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