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PDF 29LV320BTC-70 Data sheet ( Hoja de datos )
| Número de pieza | 29LV320BTC-70 | |
| Descripción | MX29LV320 | |
| Fabricantes | ETC | |
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MX29LV320T/B
32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Low Power Consumption
• 4,194,304 x 8 / 2,097,152 x 16 switchable
- Low active read current: 10mA (typical) at 5MHz
• Sector Structure
- Low standby current: 200nA (typical)
- 8K-Byte x 8 and 64K-Byte x 63
• Minimum 100,000 erase/program cycle
• Extra 64K-Byte sector for security
• 10-year data retention
- Features factory locked and identifiable, and cus-
tomer lockable
SOFTWARE FEATURES
• Twenty-Four Sector Groups
• Erase Suspend/ Erase Resume
- Provides sector group protect function to prevent pro-
- Suspends sector erase operation to read data from
gram or erase operation in the protected sector group
or program data to another sector which is not being
- Provides chip unprotect function to allow code chang-
erased
ing • Status Reply
- Provides temporary sector group unprotect function
- Data polling & Toggle bits provide detection of pro-
for code changing in previously protected sector groups
gram and erase operation completion
• Single Power Supply Operation
• Support Common Flash Interface (CFI)
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
HARDWARE FEATURES
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Ready/Busy (RY/BY) Output
• Low Vcc write inhibit is equal to or less than 1.4V
- Provides a hardware method of detecting program
• Compatible with JEDEC standard
andwww.DataSheet4U.com erase operation completion
- Pinout and software compatible to single power sup- • Hardware Reset (RESET) Input
ply Flash
- Provides a hardware method to reset the internal state
PERFORMANCE
• High Performance
- Fast access time: 70/90/120ns
machine to read mode
• WP/ACC input pin
- Provides accelerated program capability
- Fast program time: 7us/word typical utilizing acceler-
ate function
- Fast erase time: 1.6s/sector, 112s/chip (typical)
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP
GENERAL DESCRIPTION
The MX29LV320T/B is a 32-mega bit Flash memory or-
ganized as 4M bytes of 8 bits and 2M words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV320T/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29LV320T/B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV320T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV320T/B uses a command register to manage
this functionality.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
P/N:PM0742
REV. 1.4, JUL. 04, 2003
1
1 page  
MX29LV320T/B
Table 1.a: MX29LV320T SECTOR GROUP ARCHITECTURE
Sector
Group
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
Sector Address
A20-A12
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
Sector Size
(Kbytes/Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
(x8)
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
P/N:PM0742
5
(x16)
Address Range
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
REV. 1.4, JUL. 04, 2003
5 Page 
MX29LV320T/B
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device
data outputs.The device remains enabled for read access
until the command register contents are altered.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory
, the system must drive WE and CE to VIL, and OE to
VIH.
An erase operation can erase one sector, multiple sectors
, or the entire device.Table 1 indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 3 defines the valid register command
sequences.Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the Automatic Select command
sequence, the device enters the Automatic Select mode.
The system can then read Automatic Select codes from
the internal register (which is separate from the memory
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Automatic Select Mode and
Automatic Select Command Sequence section for more
information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through
the WP/ACC function. If the system asserts VHH on ACC
pin, the device will provide the fast programming time to
user. This function is primarily intended to allow faster
manufacturing throughput during production. Removing
VHH from the WP/ACC pin returns the device to normal
operation. Note that the WP/ACC pin must not be at V
HH
for operations other than accelerated programming, or
device damage may result.
STANDBY MODE
MX29LV320T/B can be set into Standby mode with two
different approaches. One is using both CE and RESET
pins and the other one is using RESET pin only.
When using both pins of CE and RESET, a CMOS
Standby mode is achieved with both pins held at Vcc ±
0.3V. Under this condition, the current consumed is less
than 0.2uA (typ.). If both of the CE and RESET are held
at VIH, but not within the range of VCC ± 0.3V, the device
will still be in the standby mode, but the standby current
will be larger. During Auto Algorithm operation, Vcc ac-
tive current (ICC2) is required even CE = "H" until the
operation is completed.The device can be read with stan-
dard access time (tCE) from either of these standby
modes.
When using only RESET, a CMOS standby mode is
achieved with RESET input held at Vss ± 0.3V, Under
this condition the current is consumed less than 1uA
(typ.). Once the RESET pin is taken high,the device is
back to active without recovery delay.
In the standby mode the outputs are in the high imped-
ance state, independent of the OE input.
MX29LV320T/B is capable to provide the Automatic
Standby Mode to restrain power consumption during read-
out of data. This mode can be used effectively with an
application requested low power consumption such as
handy terminals.
To active this mode, MX29LV320T/B automatically switch
themselves to low power mode when MX29LV320T/B
addresses remain stable during access time of
tACC+30ns. It is not necessary to control CE, WE, and
OE on the mode. Under the mode, the current consumed
is typically 0.2uA (CMOS level).
P/N:PM0742
REV. 1.4, JUL. 04, 2003
11
11 Page | ||
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| PDF Descargar | [ Datasheet 29LV320BTC-70.PDF ] | |
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