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Dallas Semiconducotr - Nonvolatile Timekeeping RAM

Numéro de référence DS1642
Description Nonvolatile Timekeeping RAM
Fabricant Dallas Semiconducotr 
Logo Dallas Semiconducotr 





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DS1642 fiche technique
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DS1642
Nonvolatile Timekeeping RAM
FEATURES
§ Integrated NV SRAM, real time clock,
crystal, power fail control circuit and lithium
energy source
§ Standard JEDEC bytewide 2K x 8 static RAM
pinout
§ Clock registers are accessed identically to the
static RAM. These registers are resident in the
eight top RAM locations
§ Totally nonvolatile with over 10 years of
operation in the absence of power
§ Access times of 70 ns and 100 ns
§ Quartz accuracy ±1 minute a month @ 25°C,
factory calibrated
§ BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
§ Power-fail write protection allows for ±10%
VCC power supply tolerance
§ Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
PIN ASSIGNMENT
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
PIN DESCRIPTION
A0-A10
- Address Input
CE - Chip Enable
OE - Output Enable
WE
VCC
GND
DQ0-DQ7
- Write Enable
- +5 Volts
- Ground
- Data Input/Output
ORDERING INFORMATION
DS1642-70 70 ns access
DS1642-100 100 ns access
DESCRIPTION
The DS1642 is a 2K x 8 nonvolatile static RAM and a full-function real time clock which are both
accessible in a bytewide format. The nonvolatile time keeping RAM is pin- and function-equivalent to
any JEDEC standard 2K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets, providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid
access of incorrect data that can occur during clock update cycles. The double-buffered system also
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