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PDF ADP3189 Data sheet ( Hoja de datos )
| Número de pieza | ADP3189 | |
| Descripción | Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3189 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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8-Bit Programmable 2- to 5-Phase
Synchronous Buck Controller
ADP3189
FEATURES
Selectable 2-, 3-, 4-, or 5-phase operation at up
to 1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external
high-power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output— supports
both VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP31891 is a highly efficient multi-phase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between 0.5 V
and 1.6 V.
This device uses a multi-mode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
4-, or 5-phase operation, allowing for the construction of up to
five complementary buck switching stages.
The ADP3189 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current, so it is optimally positioned for a system transient.
The ADP3189 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
ADP3189 is specified over the extended commercial tem-
perature range of 0°C to +85°C and is available in a
40-lead LFCSP package.
1 Protected by U.S. Patent Number 6,683,441; others pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
CURRENT BALANCE AMPLIFIER
Common Mode Range
Input Resistance
Input Current
Input Current Matching
CURRENT LIMIT COMPARATOR
Output Voltage
Output Current
Maximum Output Current2
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY TIMER
Normal Mode Output Current
Output Current in Current Limit
Threshold Voltage
SOFT START
Output Current
ENABLE INPUT
Threshold Voltage
Hysteresis
Input Current
Delay Time
OD OUTPUT
Output Low Voltage
Output High Voltage
THERMAL THROTTLING CONTROL
TTSENSE Voltage Range
TTSENSE VRFAN Threshold Voltage
TTSENSE VRHOT Threshold Voltage
TTSENSE Hysteresis
TTSENSE Input Current
VRFAN Output Low Voltage
VRHOT Output Low Voltage
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
During Soft Start2
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
PWM OUTPUTS
Output Low Voltage
Output High Voltage
Symbol Conditions
VSW(X)CM
RSW(X)
ISW(X)
ΔISW(X)
SWx = 0 V
SWx = 0 V
SWx = 0 V
VILIMIT
IILIMIT
RILIMIT = 143 kΩ
RILIMIT = 143 kΩ
VCL VCSREF − VCSCOMP, RILIMIT = 143 kΩ
VCL/IILIMIT
IDELAY
IDELAY(CL)
VDELAY(TH)
ISS During start-up
VTH(EN)
VHYS(EN)
IIN(EN)
tDELAY(EN)
EN > 950 mV, CDELAY = 10 nF
VOL(OD)
VOH(OD)
Internally limited
VOL(VRFAN)
VOL(VRHOT)
I VRFAN (SINK) = −4 mA
I VRHOT (SINK) = −4 mA
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to nominal DAC output
Relative to nominal DAC output
IPWRGD(SINK) = −4 mA
CDELAY = 10 nF
VCROWBAR
tCROWBAR
Relative to nominal DAC output
Relative to FBRTN
Overvoltage to PWM going low
VOL(PWM)
VOH(PWM)
IPWM(SINK) = −400 μA
IPWM(SOURCE) = 400 μA
Rev. 0 | Page 5 of 36
ADP3189
Min Typ Max Unit
−600
35
2.5
−5
50
4.0
+200
65
5.5
+5
mV
kΩ
μA
%
1.6 1.7 1.8 V
12 μA
60 μA
105 120 135 mV
10 mV/μA
12 15 18 μA
3.0 3.75 4.5 μA
1.6 1.7 1.8 V
12 15 18 μA
800 850 900 mV
80 100 120 mV
−1 +1 μA
2 ms
100 500 mV
45
V
0
1.08
780
−105
1.11
810
55
−120
150
150
5.3
1.14
840
−135
300
300
V
V
mV
mV
μA
mV
mV
−200
100
−250
150
150
−300
200
300
mV
mV
mV
2 ms
100 400
μs
200 ns
100 150 200 mV
320 375 430 mV
100 400
400
μs
ns
160 500 mV
4.0 5
V
5 Page 
TYPICAL PERFORMANCE CHARACTERISTICS
5.0k
4.5k
4.0k
3.5k
3.0k
2.5k
2.0k
1.5k
1.0k
0.5k
0
0 200
500
Rt (kΩ)
800
Figure 6. Master Clock Frequency vs. RT
1000
ADP3189
5.0k
4.5k
4.0k
3.5k
3.0k
2.5k
2.0k
1.5k
1.0k
0.5k
0
5.8 6.0 6.2 6.4
SUPPLY CURRENT (μA)
Figure 7. Oscillator Frequency vs .Supply Current
6.6
Rev. 0 | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3189.PDF ] | |
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