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PDF AD5258 Data sheet ( Hoja de datos )
| Número de pieza | AD5258 | |
| Descripción | 64-Position Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Nonvolatile, I2C-Compatible
64-Position, Digital Potentiometer
FEATURES
Nonvolatile memory maintains wiper settings
64-position
Compact MSOP-10 (3 mm × 4.9 mm) package
I2C®-compatible interface
VLOGIC pin provides increased interface flexibility
End-to-end resistance 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time <1 ms
Software write protect command
Three-state Address Decode Pins AD0 and AD1 allow
9 packages per bus
100-year typical data retention at 55°C
Wide operating temperature −40°C to +85°C
3 V to 5 V single supply
APPLICATIONS
LCD panel VCOM adjustment
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings
GENERAL DESCRIPTION
The AD5258 provides a compact, nonvolatile 3 mm × 4.9 mm
packaged solution for 64-position adjustment applications.
These devices perform the same electronic adjustment function
as mechanical potentiometers1 or variable resistors, but with
enhanced resolution and solid-state reliability.
The wiper settings are controllable through an I2C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM providing an end-to-end tolerance accuracy of 0.1%.
There is also a software write protection function that ensures
data cannot be written to the EEPROM register.
A separate VLOGIC pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to nine devices on the same bus.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
AD5258
FUNCTIONAL BLOCK DIAGRAMS
VDD
VLOGIC
GND
SCL
SDA
AD0
AD1
RDAC
EEPROM
RDAC
REGISTER
RDAC
I2C
SERIAL
INTERFACE
POWER-
ON RESET
6 DATA
6 CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL LOGIC
AD5258
A
W
B
VLOGIC
Figure 1. Block Diagram
VDD
SCL
SDA
AD0
AD1
GND
EEPROM
I2C
SERIAL
INTERFACE
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
RDAC
REGISTER
AND
LEVEL
SHIFTER
Figure 2. Block Diagram Showing Level Shifters
A
W
B
CONNECTION DIAGRAM
W1
10 A
AD0 2 AD5258 9 B
AD1 3 TOP VIEW 8 VDD
SDA 4 (Not to Scale) 7 GND
SCL 5
6 VLOGIC
Figure 3. Pinout
1 The terms digital potentiometer, VR (variable resistor), and RDAC are used
interchangeably.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD5258
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START
Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at Power On1
EEPROM Data Restoring Time upon Restore
Command1
EEPROM Data Rewritable Time2
FLASH/EE MEMORY RELIABILITY
Endurance3
Data Retention4
Symbol
Conditions
Min Typ Max Unit
fSCL 0 400 kHz
t1 1.3 µs
t2 After this period, the first clock pulse is 0.6
generated.
µs
t3 1.3 µs
t4 0.6 µs
t5 0.6 µs
t6 0 0.9
t7 100
t8 300
t9 300
t10 0.6
tEEMEM_STORE
26
tEEMEM_RESTORE1
VDD rise time dependant. Measure
without decoupling capacitors at VDD and
GND.
300
tEEMEM_RESTORE2 VDD = 5 V.
300
µs
ns
ns
ns
µs
ms
µs
µs
tEEMEM_REWRITE
540 µs
100 700
100
kCycles
Years
1 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
2 Delay time after power-on PRESET prior to writing new EEPROM data.
3 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
SCL
t8 t9
t6
t2 t3
t4 t5 t7
t8 t9
SDA
t1
PS
Figure 4. I2C Interface Timing Diagram
t10
P
Rev. 0 | Page 5 of 24
5 Page 
0
–6 20H
–12 10H
–18 08H
–24 04H
02H
–30
01H
–36
–42
–48
–54
–60
1k
10k 100k
FREQUENCY (Hz)
Figure 24. Gain vs. Frequency vs. Code, RAB = 50 kΩ
1M
0
20H
–6
10H
–12
08H
–18
04H
–24
02H
–30
01H
–36
–42
–48
–54
–60
1k
10k 100k
FREQUENCY (Hz)
Figure 25. Gain vs. Frequency vs. Code, RAB = 100 kΩ
1M
10k
VDD = VLOGIC = 5V
1k
VDD = VLOGIC = 3V
100
10
01234
VIH (V)
Figure 26. Logic Supply Current vs. Input Voltage
5
AD5258
80
CODE = MIDSCALE, VA = VLOGIC, VB = 0V
PSRR @ VLOGIC = 5V DC ± 10% p-p AC
60
40
PSRR @ VLOGIC = 3V DC ± 10% p-p AC
20
0
100 1k 10k 100k
FREQUENCY (Hz)
Figure 27. PSRR vs. Frequency
1M
VW
1
SCL
2
400ns/DIV
Figure 28. Digital Feedthrough
VW
1
1µs/DIV
Figure 29. Midscale Glitch, Code 0×7F to 0×80
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5258.PDF ] | |
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