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PDF DM9601 Data sheet ( Hoja de datos )
| Número de pieza | DM9601 | |
| Descripción | USB to Ethernet MAC Controller | |
| Fabricantes | Davicom Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DM9601 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
1. General Description
The DM9601 is a fully integrated and cost-effective
single chip USB to Fast Ethernet MAC controller with
10/100 PHY. It is designed with the low power and
high performance process. It is a 3.3V device with 5V
tolerance and it supports 3.3V and 5V signaling.
The DM9601 provides USB transceiver which is compliant
with USB1.1, 10/100M PHY, MAC controller, memory
controller and an external MII interface, to connect
HPNA device or other transceivers that support MII
interface. This chip already integrates into 16K byte
SRAM. The DM9601 has interfaces to the UTP3, 4, 5 in
10Base-T and UTP5 in 100Base-TX. It is fully compliant with
the IEEE 802.3u Spec. Its auto-negotiation function will
automatically configure the DM9601 to take the maximum
advantage of its abilities. The DM9601 also supports IEEE
802.3x full-duplex flow control.
The DM9601 supports 3 wake-up event to wake-up system
from suspend mode. There are 7 GPIO pins (General
purpose I/O) for user’s application.
2. Block Diagram
TX+/-
RX+/-
LED
PHYceiver
100 Base-TX
transceiver
100 Base-TX
PCS
10 Base-T
Tx/Rx
External MII
Interface
EEPROM
Interface
MAC
TX Machine
MII
Control &Status
Registers
RX Machine
Memory
Management
Autonegotiation
MII Management
Control
& MII Register
Internal
SRAM
DP
DM
Final
Version: DM9601-DS-F01
June 22, 2002
1
1 page  
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
4. Pin Configuration: 100 Pin LQFP & with MII Interface Mode
AGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
GPIO4
GPIO5
GPIO6
NC
NC
NC
NC
NC
DVDD
NC
NC
NC
NC
NC
NC
NC
NC
DGND
NC
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DM9601
50 TXD0
49 TX_CLK
48 TEST5
47 RX_CLK
46 RX_ER
45 RX_DV
44 COL
43 CRS
42 DGND
41 RXD3
40 RXD2
39 RXD1
38 RXD0
37 LINK_I
36 DVDD
35 AVDD
34 TXO-
33 TXO+
32 AGND
31 AGND
30 RX-
29 RX+
28 AVDD
27 AVDD
26 BGRES
Final
Version: DM9601-DS-F01
June 22, 2002
5
5 Page 
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
7.2 Memory Type
These kinds of commands are valid when the bit
“MEM_MODE “ is set, otherwise the device will
respond with request error when receiving these
commands.
READ_MEMORY( )
Setup Stage
BmReqType Breq
Byte 0
Byte 1
C0H
02H
Wvalue
Byte 2 Byte 3
00H 00H
Windex
Byte 4
Byte 5
MemOff[7:0] MemOff[15:8]
wLength
Byte 6 Byte 7
BC[7:0] 00H
WRITE_MEMORY( )
Setup Stage
BmReqType BReq
Byte 0 Byte 1
40H 05H
Wvalue
Byte 2 Byte 3
00H 00H
Windex
Byte 4
Byte 5
MemOff[7:0] MemOff[15:8]
wLength
Byte 6 Byte 7
BC[7:0]
00H
WRITE1_MEMORY( )
Setup Stage
BmReqType Breq
Wvalue
Byte 0 Byte 1 Byte 2 Byte 3
40H 07H Data[7:0] 00H
Windex
Byte 4
Byte 5
MemOff[7:0] MemOff[15:8]
wLength
Byte 6 Byte 7
0000H
Note:
There are advantages (for USB 1.1) when we define
“WRITE_XXXXX” and “WRITER1_XXXXX” as two
different commands. There will be only “set up stage”
and “status stage”, but no “data stage” in USB bus for
WRITE1_XXXXX command.
Final
Version: DM9601-DS-F01
June 22, 2002
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9601.PDF ] | |
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