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What is SAFC164CM?

This electronic component, produced by the manufacturer "Infineon Technologies", performs the same function as "16-Bit CMOS Microcontroller".


SAFC164CM Datasheet PDF - Infineon Technologies

Part Number SAFC164CM
Description 16-Bit CMOS Microcontroller
Manufacturers Infineon Technologies 
Logo Infineon Technologies Logo 


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Total 30 Pages



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User’s Manual, V1.0, Feb. 2002
C164CM/SM
16-Bit Single-Chip Microcontroller
Microcontrollers
Never stop thinking.

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SAFC164CM equivalent
C164CM/C164SM
Derivatives
Table of Contents
Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
2
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Big Performance in a Small Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . 2-3
High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . 2-4
Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . 2-8
On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
3
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Internal ROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Protection of the On-Chip Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
OTP Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Selecting an OTP Programming Mode . . . . . . . . . . . . . . . . . . . . . . . 3-14
OTP Module Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Read Protection Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
4 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2 Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3 Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.4 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.5 CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
5
5.1
5.1.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . 5-15
Saving Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
User’s Manual I-1 V1.0, 2002-02


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