PDF ICM7170 Data sheet ( Hoja de datos )

Número de pieza	ICM7170
Descripción	Microprocessor-Compatible / Real-Time Clock
Fabricantes	Intersil Corporation
Logotipo
Hay una vista previa y un enlace de descarga de ICM7170 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas
No Preview Available ! ICM7170 August 1997 Microprocessor-Compatible, Real-Time Clock [ /Title (ICM7 170) /Sub- ject (Micro proces- sor- Com- pati- ble, Real- Time Clock) /Autho r () /Key- words (Inter- sil Corpo- ration, Real Time Clock, Bat- tery Backu p, Inter- nal Oscil- lator, Micro- proces- sor inter- face, Data Features Description • 8-Bit, µP Bus Compatible - Multiplexed or Direct Addressing • Regulated Oscillator Supply Ensures Frequency Stability and Low Power • Time From 1/100 Seconds to 99 Years • Software Selectable 12/24 Hour Format • Latched Time Data Ensures No Roll Over During Read • Full Calendar with Automatic Leap Year Correction • On-Chip Battery Backup Switchover Circuit • Access Time Less than 300ns • 4 Programmable Crystal Oscillator Frequencies Over Industrial Temperature Range • 3 Programmable Crystal Oscillator Frequencies Over Military Temperature Range • On-Chip Alarm Comparator and RAM • Interrupts from Alarm and 6 Selectable Periodic Intervals • Standby Micro-Power Operation: 1.2µA Typical at 3.0V and 32kHz Crystal Applications • Portable and Personal Computers • Data Logging • Industrial Control Systems • Point Of Sale Ordering Information TEMP. RANGE PART NUMBER (oC) PACKAGE ICM7170IPG -40 to 85 24 Ld PDIP PKG. NO. E24.6 The ICM7170 real time clock is a microprocessor bus compatible peripheral, fabricated using Intersil’s silicon gate CMOS LSl process. An 8-bit bidirectional bus is used for the data I/O circuitry. The clock is set or read by accessing the 8 internal separately addressable and programmable counters from 1/100 seconds to years. The counters are controlled by a pulse train divided down from a crystal oscillator circuit, and the frequency of the crystal is selectable with the on- chip command register. An extremely stable oscillator frequency is achieved through the use of an on-chip regulated power supply. The device access time (tACC) of 300ns eliminates the need for wait states or software overhead with most microprocessors. Furthermore, an ALE (Address Latch Enable) input is provided for interfacing to microprocessors with a multiplexed address/data bus. With these two special features, the ICM7170 can be easily interfaced to any available microprocessor. The ICM7170 generates two types of interrupts, periodic and alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be programmed by the internal interrupt control register to provide 6 different output signals. The alarm interrupt is set by loading an on-chip 51-bit RAM that activates an interrupt output through a comparator. The alarm interrupt occurs when the real time counter and alarm RAM time are equal. A status register is available to indicate the interrupt source. An on-chip Power Down Detector eliminates the need for external components to support the battery back-up function. When a power down or power failure occurs, internal logic switches the on-chip counters to battery back- up operation. Read/write functions become disabled and operation is limited to time-keeping and interrupt generation, resulting in low power consumption. Internal latches prevent clock roll-over during a read cycle. Counter data is latched on the chip by reading the 100th-seconds counter and is held indeﬁnitely until the counter is read again, assuring a stable and reliable time value. ICM7170IDG -40 to 85 24 Ld SBDIP D24.6 ICM7170IBG -40 to 85 24 Ld SOIC M24.3 ICM7170MDG -55 to 125 24 Ld SBDIP D24.6 ICM7170AIPG -40 to 85 24 Ld PDIP E24.6 ICM7170AIDG -40 to 85 24 Ld SBDIP D24.6 ICM7170AIBG -40 to 85 24 Ld SOIC M24.3 ICM7170AMDG -55 to 125 24 Ld SBDIP D24.6 NOTE: “A” Parts Screened to <5µA ISTBY at 32kHz. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 12-5 File Number 3019.3 1 page Timing Diagrams ICM7170 A0 - A4, CS RD ADDRESS VALID, CS LOW tAS tCYC tRD tAR D0 - D7 tACC OUTPUT DATA VALID tRX FIGURE 1. READ CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH, WR = VIH) A0 - A4, CS WR D0 - D7 ADDRESS VALID, CS LOW tAD tWA tCYC tWL tDW tWD INPUT DATA VALID FIGURE 2. WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH, RD = VIH) A0 - A4, D0 - D7, CS ALE RD ADDRESS VALID, CS LOW tLA tLL tACC OUTPUT DATA VALID tAR tAL tCYC tAS tRD FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS (WR = VIH) 12-9 5 Page ICM7170 TABLE 5. TYPICAL LOAD CAPACITOR VALUES CRYSTAL FREQUENCY LOAD CAPS (C1, C2) TRIMMER CAP (C3) 32kHz 33pF 5 - 50pF 1MHz 33pF 5 - 50pF 2MHz 25pF 5 - 50pF 4MHz 22pF 5 - 100pF This three capacitor tuning method will be more stable than the original design and is mandatory for 32kHz tuning fork crystals: without it they may leap into an overtone mode when power is initially applied. The original two-capacitor circuit (Figure 8) will continue to work as well as it always has, and may continue to be used in applications where cost or space is a critical consideration. It is also easier to tune to frequency since one end of the trimmer capacitor is ﬁxed at the AC ground of the circuit (VDD), minimizing the disturbance cause by contact between the adjustment tool and the trimmer capacitor. Note that in both conﬁgurations the load capacitors are connected between the oscillator pins and VDD - do not use VSS as an AC ground. Layout: Due to the extremely low current (and therefore high impedance) design of the ICM7170s oscillator, special attention must be given to the layout of this section. Stray capacitance should be minimized. Keep the oscillator traces on a single layer of the PCB. Avoid putting a ground plane above or below this layer. The traces between the crystal, the capacitors, and the ICM7170 OSC pins should be as short as possible. Completely surround the oscillator components with a thick trace of VDD to minimize coupling with any digital signals. The ﬁnal assembly must be free from contaminants such as solder ﬂux, moisture, or any other potential sources of leakage. A good solder mask will help keep the traces free of moisture and contamination over time. Oscillator Tuning Trimming the oscillator should be done indirectly. Direct monitoring of the oscillator frequency by probing OSC IN or OSC OUT is not accurate due to the capacitive loading of most probes. One way to accurately trim the ICM7170 is by turning on the 1 second periodic interrupt and trimming the oscillator until the interrupt period is exactly one second. This can be done as follows: 1. Turn on the system. Write a 00H to the Interrupt Mask Register (location 10H) to clear all interrupts. 2. Set the Command Register (location 11H) for the appropriate crystal frequency, set the Interrupt Enable and Run/Stop bits to 1, and set the Test bit to 0. 3. Write a 08H to the Interrupt Mask Register to turn on the 1s interrupt. 4. Write an interrupt handler to read the Interrupt Status Register after every interrupt. This resets the interrupt and allows it to be set again. A software loop that reads the Interrupt Status Register several times each second will accomplish this also. 5. Connect a precision period counter capable of measuring 1s within the accuracy desired to the interrupt output. If the interrupt is conﬁgured as active low, trigger on the falling edge. If the interrupt is active high, trigger on the rising edge. Be sure to measure the period between when the transistor turns ON, and when the transistor turns ON a second later. 6. Adjust C3 (C2 for the two-capacitor load conﬁguration) for an interrupt period of exactly 1.000000 seconds. Application Notes Digital Input Termination During Backup To ensure low current drain during battery backup operation, none of the digital inputs to the ICM7170 should be allowed to ﬂoat. This keeps the input logic gates out of their transition region, and prevents crossover current from ﬂowing which will shorten battery life. The address, data, CS, and ALE pins should be pulled to either VDD or VSS, and the RD and WR inputs should be pulled to VDD. This is necessary whether the internal battery switchover circuit is used or not. IBM/PC Evaluation Circuit Figure 9 shows the schematic of a board that has been designed to plug into an IBM PC/XT (Note 1) or compatible computer. In this example CS is permanently tied low and access to the chip is controlled by the RD and WR pins. These signals are generated by U1, which gates the IBM’s lOR and lOW with a device select signal from U3, which is functioning as an I/O block address decoder. DS1 selects the interrupt priority. U5 is used to isolate the ICM7170 from the PC databus for test purposes. It is only required on heavily-loaded TTL databuses - the ICM7170 can drive most TTL and CMOS databuses directly. Since the IBM PC/XT (Note 1) requires a positive interrupt transition, the ICM7170s interrupt output transistor has been conﬁgured as a source follower. As a source follower, the interrupt output signal will swing between 0V and 2.5V. When trimming the oscillator, the frequency counter must be triggered on the rising edge of the interrupt signal. TABLE 6. BATTERIES CRYSTALS Panasonic Saronix 32kHz NTF3238 Rayovac Statek 32kHz CX - 1V Seiko 2MHz GT - 38 NOTE: 1. IBM, IBM PC, and IBM XT are trademarks of IBM Corp. 12-15 11 Page

Páginas	Total 13 Páginas
PDF Descargar	[ Datasheet ICM7170.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ICM7170	Microprocessor-Compatible / Real-Time Clock	Intersil Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar