|
|
PDF KMM5364005CK Data sheet ( Hoja de datos )
| Número de pieza | KMM5364005CK | |
| Descripción | (KMM5364105CK / KMM5364005CK) 4MBx36 DRAM Simm Using 4MBx4 And 16MB Quad Cas | |
| Fabricantes | Samsung Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de KMM5364005CK (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
DRAM MODULE
KMM5364005CK/CKG
KMM5364105CK/CKG
KMM5364005CK/CKG & KMM5364105CK/CKG Fast Page Mode with EDO Mode
4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K, Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM53640(1)05CK is a 4Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM53640(1)05CK consists of eight CMOS 4Mx4bits DRAMs
in 24-pin SOJ package and one CMOS 4Mx4 bit Quad CAS
with EDO DRAM in 28-pin SOJ package mounted on a 72-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM53640(1)05CK is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
tHPC
-5
50ns
13ns
90ns
25ns
-6
60ns
15ns 110ns 30ns
FEATURES
• Part Identification
- KMM5364005CK(4096 cycles/64ms Ref, SOJ, Solder)
- KMM5364005CKG(4096 cycles/64ms Ref, SOJ, Gold)
- KMM5364105CK(2048 cycles/32ms Ref, SOJ, Solder)
- KMM5364105CKG(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode with Extended Data Out
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
• PCB : Height(1000mil), single sided component
PIN CONFIGURATIONS
Pin Symbol Pin Symbol
1 VSS 37 DQ17
2
DQ0
38 DQ35
3
DQ18
39
Vss
4
DQ1
40 CAS0
5 DQ19 41 CAS2
6
DQ2
42 CAS3
7 DQ20 43 CAS1
8
DQ3
44 RAS0
9
DQ21
45 Res(RAS1)
10 Vcc 46
NC
11 NC 47
W
12 A0 48 NC
13 A1 49 DQ9
14 A2 50 DQ27
15 A3 51 DQ10
16 A4 52 DQ28
17 A5 53 DQ11
18 A6 54 DQ29
19 A10 55 DQ12
20 DQ4 56 DQ30
21 DQ22 57 DQ13
22 DQ5 58 DQ31
23 DQ23 59
Vcc
24 DQ6 60 DQ32
25 DQ24 61 DQ14
26 DQ7 62 DQ33
27 DQ25 63 DQ15
28 A7 64 DQ34
29 A11 65 DQ16
30 Vcc 66
NC
31 A8 67 PD1
32 A9 68 PD2
33 Res(RAS1) 69
PD3
34 RAS0 70
PD4
35 DQ26 71
NC
36 DQ8 72
Vss
PIN NAMES
Pin Name
A0 - A11
A0 - A10
DQ0 - DQ35
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs(4K Ref)
Address Inputs(2K Ref)
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1 Vss Vss
PD2 NC
NC
PD3 Vss
NC
PD4 Vss
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
* NOTE : A11 is used for only KMM5364005CK/CKG (4K ref.)
1 page  
DRAM MODULE
KMM5364005CK/CKG
KMM5364105CK/CKG
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF
Parameter
CAS precharge time (C-B-R counter test
Access time from CAS precharge
Hyper page mode cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width(Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width (Hyper Page Cycle)
Hold time CAS low to CAS high
Symbol
tCPT
tCPA
tHPC
tCP
tRASP
tRHCP
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tWPE
tCLCH
-5
Min Max
20
30
25
8
50 200K
30
10
10
5
3 13
3 13
15
5
5
Min
20
30
10
60
35
10
10
5
3
3
15
5
5
-6
Max
35
200K
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
3
13
6,11,12
6,11
14
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between VIH(min) and VIL(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
4. Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
5. Assumes that tRCD≥tRCD(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
12. If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit cond-
tion of the output is achieved by RAS high going.
13. tASC≥tCP min
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS≥tWCS(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
14. In order to hold the address latched by the first CAS going
low, the parameter tCLCH must be met.
5 Page 
DRAM MODULE
HIDDEN REFRESH CYCLE ( READ )
KMM5364005CK/CKG
KMM5364105CK/CKG
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VOH -
DQ
VOL -
tRC
tRAS
tRP tRC
tRAS
tCRP
tRCD
tRSH
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCS
tRRH
tCHR
tWRH
tWRP
tRP
OPEN
tAA
tCLZ
tRAC
tCAC
tREZ
tWEZ
DATA-OUT
tCEZ
Don′t care
Undefined
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet KMM5364005CK.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KMM5364005CK | (KMM5364105CK / KMM5364005CK) 4MBx36 DRAM Simm Using 4MBx4 And 16MB Quad Cas | Samsung Semiconductor |
| KMM5364005CSW | 4MB X 36 DRAM Simm Using 4MB X 16 & Quad Cas 4MB X 4 | Samsung Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |