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PDF HMS30C7202N Data sheet ( Hoja de datos )

Número de pieza HMS30C7202N
Descripción 32-Bit MPU
Fabricantes MagnaChip Semiconductor　
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No Preview Available ! HMS30C7202N Hoja de datos, Descripción, Manual

HMS30C7202N
Highly-integrated MPU
(ARM Based 32-Bit Microprocessor)
Datasheet
Version 1.1
MagnaChip Semiconductor Ltd.

1 page




HMS30C7202N pdf
HMS30C7202N
FEATURES
„ 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz
„ 8Kbytes combined instruction/data cache
„ Memory management unit
„ Supports Little Endian operating system
„ 2Kbytes SRAM for internal buffer memory
„ On-chip peripherals with individual power-down:
- Multi-channel DMA
- 4 Timer Channels with Watch Dog Timer
- Intelligent Interrupt Controller
- Memory controller for ROM, Flash, SRAM, SDRAM
- Power management unit
- LCD Controller for mono/color STN and TFT LCD
- Real-time clock (32.768kHz oscillator)
- Infrared communications (SIR support)
- 4 UARTs (16C550 compatible)
- PS/2 External Keyboard / Mouse interface
- 2 Pulse-Width-Modulated (PWM) interface
- Matrix Keyboard control interface (8*8)
- GPIO
- MMC / SMC Card interface
- USB (slave)
- On-chip ADC and interface module (Battery Check, Audio In, Touch Panel)
- On-chip DAC and interface module (8 Bit Stereo Audio Output)
- 3 PLLs
Figure A. Functional Block Diagram
„ JTAG debug interface and boundary scan
„ 0.25um Low Power CMOS Process
„ 2.5V internal / 3.3V IO supply voltage
„ 256-pin MQFP / FBGA package
„ Low power consumption
© 2004 MagnaChip Semiconductor Ltd. All Rights Reserved.
-v-
Version 1.1

5 Page





HMS30C7202N arduino
HMS30C7202N
10.2.2.25 DDATA............................................................................................................................................. 106
10.2.2.26 DDIR ................................................................................................................................................ 106
10.2.2.27 DMASK............................................................................................................................................ 106
10.2.2.28 DBSTAT ........................................................................................................................................... 106
10.2.2.29 DEDGE ............................................................................................................................................ 106
10.2.2.30 DCLK ............................................................................................................................................... 106
10.2.2.31 DPOL................................................................................................................................................ 106
10.2.2.32 GPIO PORT D Enable Register ........................................................................................................ 106
10.2.2.33 EDATA ............................................................................................................................................. 107
10.2.2.34 EDIR................................................................................................................................................. 107
10.2.2.35 EMASK ............................................................................................................................................ 107
10.2.2.36 EBSTAT............................................................................................................................................ 107
10.2.2.37 EEDGE............................................................................................................................................. 107
10.2.2.38 ECLK................................................................................................................................................ 107
10.2.2.39 EPOL ................................................................................................................................................ 107
10.2.2.40 GPIO PORT E Enable Register ........................................................................................................ 107
10.2.2.41 Tic Test mode Register(TICTMDR) ................................................................................................. 107
10.2.2.42 PORTA Multi-function Select register(AMULSEL)......................................................................... 108
10.2.2.43 SWAP Pin Configuration Register(SWAP)....................................................................................... 108
10.2.3 GPIO Interrupt ......................................................................................................................................... 108
10.2.4 GPIO Rise/Fall Time ................................................................................................................................ 109
10.3 INTERRUPT CONTROLLER................................................................................................................................... 110
10.3.1 Block diagram .......................................................................................................................................... 110
10.3.2 Registers ................................................................................................................................................... 110
10.3.2.1 Interrupt Enable Register (IER) .........................................................................................................111
10.3.2.2 Interrupt Status Register (ISR).......................................................................................................... 112
10.3.2.3 IRQ Vector Register (IVR) ............................................................................................................... 113
10.3.2.4 Source Vector Register (SVR0 to SVR30)........................................................................................ 113
10.3.2.5 Interrupt ID Register (IDR) .............................................................................................................. 113
10.3.2.6 Priority Set Register (PSR0 to PSR7) ............................................................................................... 113
10.4 MATRIX KEYBOARD INTERFACE CONTROLLER ................................................................................................... 115
10.4.1 External Signals........................................................................................................................................ 115
10.4.2 Registers ................................................................................................................................................... 115
10.4.2.1 Keyboard Configuration Register (KBCR)....................................................................................... 116
10.4.2.2 Keyboard Scanout Register(KBSC) ................................................................................................. 116
10.4.2.3 Keyboard Test Register (KBTR)....................................................................................................... 117
10.4.2.4 Keyboard Value Register (KVR0) .................................................................................................... 117
10.4.2.5 Keyboard Value Register (KVR1) .................................................................................................... 117
10.4.2.6 Keyboard Status Register (KBSR).................................................................................................... 117
10.5 PS/2 INTERFACE CONTROLLER........................................................................................................................... 119
10.5.1 External Signals........................................................................................................................................ 119
10.5.2 Registers ................................................................................................................................................... 119
10.5.2.1 PSDATA ........................................................................................................................................... 119
10.5.2.2 PSSTAT ............................................................................................................................................ 120
10.5.2.3 PSCONF ........................................................................................................................................... 120
10.5.2.4 PSINTR ............................................................................................................................................ 121
10.5.2.5 PSTDLO ........................................................................................................................................... 121
10.5.2.6 PSTPRI ............................................................................................................................................. 121
10.5.2.7 PSTXMT .......................................................................................................................................... 122
10.5.2.8 PSTREC ........................................................................................................................................... 122
10.5.2.9 PSPWDN.......................................................................................................................................... 123
10.5.3 Application Notes ..................................................................................................................................... 123
10.6 RTC .................................................................................................................................................................. 124
10.6.1 External Signals........................................................................................................................................ 125
10.6.2 Functional Description............................................................................................................................. 125
10.6.3 Registers ................................................................................................................................................... 125
10.6.3.1 RTC Data Register (RTCDR) ........................................................................................................... 125
10.6.3.2 RTC Match Register (RTCMR) ........................................................................................................ 126
10.6.3.3 RTC Status Register (RTCS) ............................................................................................................ 126
10.6.3.4 RTC Control Register (RTCCR)....................................................................................................... 126
© 2004 MagnaChip Semiconductor Ltd. All Rig5hts Reserved.
-5-
Version 1.1

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