|
|
PDF 82865GV Data sheet ( Hoja de datos )
| Número de pieza | 82865GV | |
| Descripción | Graphics and Memory Controller Hub | |
| Fabricantes | Intel | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 82865GV (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Intel® 865G/865GV Chipset
Datasheet
Intel® 82865G/82865GV Graphics and Memory Controller Hub
(GMCH)
February 2004
Document Number: 252514-005
1 page  
3.6.6 SUBC1—Sub-Class Code Register (Device 1) ................................91
3.6.7 BCC1—Base Class Code Register (Device 1) .................................91
3.6.8 MLT1—Master Latency Timer Register (Device 1)...........................92
3.6.9 HDR1—Header Type Register (Device 1) ........................................92
3.6.10 PBUSN1—Primary Bus Number Register (Device 1) .......................92
3.6.11 SBUSN1—Secondary Bus Number Register (Device 1) ..................93
3.6.12 SUBUSN1—Subordinate Bus Number Register (Device 1) .............93
3.6.13 SMLT1—Secondary Bus Master Latency Timer Register
(Device 1)..........................................................................................93
3.6.14 IOBASE1—I/O Base Address Register (Device 1) ...........................94
3.6.15 IOLIMIT1—I/O Limit Address Register (Device 1) ............................94
3.6.16 SSTS1—Secondary Status Register (Device 1) ...............................95
3.6.17 MBASE1—Memory Base Address Register (Device 1)....................96
3.6.18 MLIMIT1—Memory Limit Address Register (Device 1).....................97
3.6.19 PMBASE1—Prefetchable Memory Base Address Register
(Device 1)..........................................................................................98
3.6.20 PMLIMIT1—Prefetchable Memory Limit Address Register
(Device 1)..........................................................................................98
3.6.21 BCTRL1—Bridge Control Register (Device 1) ..................................99
3.6.22 ERRCMD1—Error Command Register (Device 1) .........................100
3.7 Integrated Graphics Device Registers (Device 2)........................................101
3.7.1 VID2—Vendor Identification Register (Device 2) ............................102
3.7.2 DID2—Device Identification Register (Device 2) ............................102
3.7.3 PCICMD2—PCI Command Register (Device 2) .............................103
3.7.4 PCISTS2—PCI Status Register (Device 2) ....................................104
3.7.5 RID2—Revision Identification Register (Device 2) .........................104
3.7.6 CC—Class Code Register (Device 2) .............................................105
3.7.7 CLS—Cache Line Size Register (Device 2) ...................................105
3.7.8 MLT2—Master Latency Timer Register (Device 2).........................105
3.7.9 HDR2—Header Type Register (Device 2) ......................................106
3.7.10 GMADR—Graphics Memory Range Address Register
(Device 2)........................................................................................106
3.7.11 MMADR—Memory-Mapped Range Address Register
(Device 2)........................................................................................107
3.7.12 IOBAR—I/O Decode Register (Device 2) .......................................107
3.7.13 SVID2—Subsystem Vendor Identification Register
(Device 2)........................................................................................108
3.7.14 SID2—Subsystem Identification Register (Device 2)......................108
3.7.15 ROMADR—Video BIOS ROM Base Address Registers
(Device 2)........................................................................................108
3.7.16 CAPPOINT—Capabilities Pointer Register (Device 2) ...................109
3.7.17 INTRLINE—Interrupt Line Register (Device 2) ...............................109
3.7.18 INTRPIN—Interrupt Pin Register (Device 2)...................................109
3.7.19 MINGNT—Minimum Grant Register (Device 2) ..............................110
3.7.20 MAXLAT—Maximum Latency Register (Device 2) .........................110
3.7.21 PMCAPID—Power Management Capabilities Identification
Register (Device 2) .........................................................................110
3.7.22 PMCAP—Power Management Capabilities Register
(Device 2)........................................................................................111
3.7.23 PMCS—Power Management Control/Status Register
(Device 2)........................................................................................111
3.7.24 SWSMI—Software SMI Interface Register (Device 2) ....................112
Intel® 82865G/82865GV GMCH Datasheet
5
5 Page 
44 XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0 .........................214
45 XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1 .........................215
46 XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2 .........................215
47 XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3 .........................216
48 XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4 .........................216
49 XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5 .........................217
50 XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6 .........................217
51 XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7 .........................218
52 XOR Chain 8 (40 Inputs) Output Pins: SDM_A8, SDM_B8 .........................218
53 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................219
54 XOR Excluded Pins .....................................................................................220
55 Intel® 82865GV Ball List by Signal Name ....................................................231
56 XOR Chain Outputs .....................................................................................243
57 XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0 .........................244
58 XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1 .........................245
59 XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2 .........................245
60 XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3 .........................246
61 XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4 .........................246
62 XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5 .........................247
63 XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6 .........................247
64 XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7 .........................248
65 XOR Chain 8 (40 Inputs) Output Pins: HTRDY#, BPRI# .............................248
66 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................249
67 XOR Excluded Pins .....................................................................................250
Intel® 82865G/82865GV GMCH Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82865GV.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 82865G | Graphics and Memory Controller Hub | Intel |
| 82865GV | Graphics and Memory Controller Hub | Intel |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |