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PDF MC74VHC1GT126 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC1GT126 | |
| Descripción | Noninverting Buffer / CMOS Logic Level Shifter | |
| Fabricantes | ON Semiconductor | |
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MC74VHC1GT126
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3−state buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC1GT126 requires the 3−state control input (OE) to be
set Low to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT126 input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT126 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
• High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 16
OE 1
IN A 2
GND 3
5 VCC
4 OUT Y
http://onsemi.com
MARKING
DIAGRAMS
SC−88A / SOT−353/SC−70
DF SUFFIX
CASE 419A
W3d
Pin 1
d = Date Code
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
W3d
Pin 1
d = Date Code
PIN ASSIGNMENT
1 OE
2 IN A
3 GND
4 OUT Y
5 VCC
A Input
L
H
X
FUNCTION TABLE
OE Input
Y Output
HL
HH
LZ
Figure 1. Pinout (Top View)
OE
OUT Y
IN A
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2002
December, 2003 − Rev. 9
1
Publication Order Number:
MC74VHC1GT126/D
1 page  
MC74VHC1GT126
CAVITY TOP TAPE
TAPE
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
COMPONENTS
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
TAPE DIMENSIONS mm
2.00
4.00
4.00
8.00 $0.30
TAPE LEADER
NO COMPONENTS
400 mm MIN
Ğ1.50 TYP
1.75
3.50 $0.50
Ğ1.00 MIN
1
DIRECTION OF FEED
Figure 10. SC−70−5/SC−88A/SOT−353 DF1 Reel Configuration/Orientation
TAPE DIMENSIONS mm
2.00
4.00
4.00
8.00 $0.30
Ğ1.50 TYP
1.75
3.50 $0.50
Ğ1.00 MIN
1
DIRECTION OF FEED
Figure 11. SC−70/SC−88A/SOT−353 DF2 and SOT23−5/TSOP−5/SC59−5 DT1 Reel Configuration/Orientation
http://onsemi.com
5
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| PDF Descargar | [ Datasheet MC74VHC1GT126.PDF ] | |
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