PDF KMM372F410CS Data sheet ( Hoja de datos )

Número de pieza	KMM372F410CS
Descripción	DRAM Module
Fabricantes	Samsung Semiconductor
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No Preview Available ! DRAM MODULE KMM372F400CK/CS KMM372F410CK/CS KMM372F400CK/CS / KMM372F410CK/CS Fast Page with EDO Mode 4M x 72 DRAM DIMM with ECC using 4Mx4, 4K/2K Refresh, 3.3V GENERAL DESCRIPTION The Samsung KMM372F40(1)0C is a 4Mx72bits Dynamic RAM high density memory module. The Samsung KMM372F40(1)0C consists of eighteen CMOS 4Mx4bits DRAMs in SOJ/TSOP-II 300mil package, and two 16bits driver IC in 48pin TSSOP package mounted on a 168-pin glass- epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM372F40(1)0C is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. PERFORMANCE RANGE Speed -5 tRAC 50ns tCAC 18ns tRC 90ns tHPC 25ns -6 60ns 20ns 110ns 30ns FEATURES • Part Identification - KMM372F400CK (4096 cycles/64ms Ref., SOJ) - KMM372F400CS (4096 cycles/64ms Ref., TSOP) - KMM372F410CK (4096 cycles/32ms Ref., SOJ) - KMM372F410CS (4096 cycles/32ms Ref., TSOP) • Fast Page Mode with Extended Data Out Mode Operation • CAS-before-RAS Refresh capability • RAS-only and Hidden refresh capability • TTL compatible inputs and outputs • Single 3.3V±0.3V power supply • JEDEC standard pinout & Buffered PDpin • Buffered input except RAS and DQ • PCB : Height(1000mil), double sided component PIN CONFIGURATIONS PIN NAMES Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back Pin Names Function 1 VSS 29 RSVD 57 DQ22 85 VSS 113 RSVD 141 DQ58 2 DQ0 30 RAS0 58 DQ23 86 DQ36 114 RAS1 142 DQ59 A0, B0, A1 - A11 Address Input (4K Ref.) A0, B0, A1 - A10 Address Input (2K Ref.) 3 DQ1 31 OE0 59 VCC 87 DQ37 115 RFU 143 VCC DQ0 - DQ71 Data In/Out 4 DQ2 32 VSS 60 DQ24 88 DQ38 116 VSS 144 DQ60 5 DQ3 33 A0 61 RFU 89 DQ39 117 A1 145 RFU 6 VCC 34 A2 62 RFU 90 VCC 118 A3 146 RFU 7 DQ4 35 A4 63 RFU 91 DQ40 119 A5 147 RFU W0, W2 OE, OE2 RAS0, RAS2 Read/Write Enable Output Enable Row Address Strobe 8 DQ5 36 A6 64 RFU 92 DQ41 120 A7 148 RFU CAS0, CAS4 Colume Address Strobe 9 DQ6 37 A8 65 DQ25 93 DQ42 121 A9 149 DQ61 10 DQ7 38 A10 66 DQ26 94 DQ43 122 A11 150 DQ62 11 DQ8 39 A12 67 DQ27 95 DQ44 123 A13 151 DQ63 VCC VSS Power(+3.3V) Ground 12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS NC No Connection 13 DQ9 41 14 DQ10 42 15 DQ11 43 16 DQ12 44 RFU RFU VSS OE2 69 DQ28 97 DQ45 125 RFU 153 DQ64 70 DQ29 98 DQ46 126 B0 154 DQ65 71 DQ30 99 DQ47 127 VSS 155 DQ66 72 DQ31 100 DQ48 128 RFU 156 DQ67 PDE PD1 - 8 ID0 - 1 Presence Detect Enable Presence Detect ID bit 17 DQ13 45 RAS2 73 VCC 101 DQ49 129 RAS3 157 VCC 18 VCC 46 CAS4 74 DQ32 102 VCC 130 CAS5 158 DQ68 19 DQ14 47 RSVD 75 DQ33 103 DQ50 131 RSVD 159 DQ69 20 DQ15 48 W2 76 DQ34 104 DQ51 132 PDE 160 DQ70 21 DQ16 49 VCC 77 DQ35 105 DQ52 133 VCC 161 DQ71 RSVD Reserved Use RFU Reserved for Future Use Pins marked ′′ are not used in this module. PD & ID Table 22 DQ17 50 RSVD 78 23 VSS 51 RSVD 79 24 RSVD 52 DQ18 80 25 RSVD 53 DQ19 81 26 VCC 54 VSS 82 27 W0 55 DQ20 83 28 CAS0 56 DQ21 84 VSS PD1 PD3 PD5 PD7 ID0 VCC 106 DQ53 134 RSVD 162 107 VSS 135 RSVD 163 108 RSVD 136 DQ54 164 109 RSVD 137 DQ55 165 110 VCC 138 VSS 166 111 RFU 139 DQ56 167 112 *CAS1 140 DQ57 168 VSS PD2 PD4 PD6 PD8 ID1 VCC NOTE : A11 is used for only KMM372F400CK/CS (4K ref.) PD Note : PD & ID Terminals must each be pulled up through a resister to VCC at the next higher Pin PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 50NS 1 1 0 1 1 0 0 0 0 0 60NS 1 1 0 1 1 1 1 0 0 0 level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. ID : 0 for Vss & 1 for N.C 1 page DRAM MODULE KMM372F400CK/CS KMM372F410CK/CS AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Symbol RAS to W dealy time Column address to W delay time CAS precharge time to W delay time CAS set-up time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time CAS precharge time (C-B-R counter test cycle) Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time CAS precharge time(Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay time from RAS Output buffer turn off delay time from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width(Hyper page cycle) tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE -5 Min Max 71 48 53 5 8 3 20 33 25 68 8 50 200K 35 18 18 5 18 13 15 8 10 3 13 3 18 20 5 5 5 5 -6 Min Max 83 55 60 5 8 3 20 40 30 77 10 60 200K 40 20 20 5 20 15 15 8 10 3 15 3 20 20 5 5 5 5 Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive tPD 10 10 tPDOFF 2 7 2 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 7,14 7 14 14 14 3,14 12 12 14 14 14 6,11,14 14 14 14 6.11.12 6.11.14 14 ns ns 5 Page DRAM MODULE HYPER PAGE READ CYCLE KMM372F400CK/CS KMM372F410CK/CS VIH - RAS VIL - VIH - CAS VIL - VIH - A VIL - tRASP tCRP tCSH tRCD tHPC tCP tCAS ¡ó tHPC tCP tHPC tCP tRHCP tCAS tCAS tCAS tRAD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDR COLUMN ADDRESS tRP tREZ VIH - W VIL - VIH - OE VIL - VOH - DQ VOL - tRCS tCAC tAA tCPA tAA tCAC tOEA tRAC tCAC tDOH VALID DATA-OUT tOLZ tCLZ VALID DATA-OUT tCAC tAA tCPA tOCH tOEA tRCH tRRH tCPA tCAC tAA tCHO tOEP tOEP tOEZ tOEZ tOEA VALID DATA-OUT tOEZ VALID DATA-OUT Don′t care Undefined 11 Page

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