PDF T89C51CC01 Data sheet ( Hoja de datos )

Número de pieza	T89C51CC01
Descripción	Enhanced 8-Bit Microcontroller
Fabricantes	ATMEL Corporation
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Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 1K Bytes of On-chip XRAM • 32K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C Erase/Write Cycle: 100K • Boot Code Section with Independent Lock Bits • 2K Bytes of On-chip Flash for Bootloader • In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability • 2K Bytes of On-chip EEPROM Erase/Write Cycle: 100K • 14-sources 4-level Interrupts • Three 16-bit Timers/Counters • Full Duplex UART Compatible 80C51 • Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz) • Five Ports: 32 + 2 Digital I/O Lines • Five-channel 16-bit PCA with: – PWM (8-bit) – High-speed Output – Timer and Edge Capture • Double Data Pointer • 21-bit Watchdog Timer (7 Programmable Bits) • A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs • Full CAN Controller: – Fully Compliant with CAN Rev2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 15 Independent Message Objects: Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt – Supports: Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode – 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode – Readable Error Counters – Programmable Link to On-chip Timer for Time Stamping and Network Synchronization – Independent Baud Rate Prescaler – Data, Remote, Error and Overload Frame Handling • On-chip Emulation Logic (Enhanced Hook System) • Power Saving Modes: – Idle Mode – Power-down Mode 1. At BRP = 1 sampling point will be fixed. Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory T89C51CC01 AT89C51CC01 Rev. 4129N–CAN–03/08 1 1 page Read-Modify-Write Instructions Figure 2. Port 0 Structure ADDRESS LOW/ DATA CONTROL READ LATCH INTERNAL BUS WRITE TO LATCH DQ P0.X LATCH 1 0 A/T89C51CC01 VDD (2) P0.x (1) READ PIN Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain. Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL VDD READ LATCH INTERNAL BUS WRITE TO LATCH DQ P2.X LATCH 1 0 INTERNAL PULL-UP (2) P2.x (1) READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle. When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line. Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called "Read- Modify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: 4129N–CAN–03/08 5 5 Page A/T89C51CC01 Table 9. CAN SFRs (Continued) Mnemonic Add Name 76543210 CANEN1 CEh CAN Enable Channel byte 1 – ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8 CANEN2 CFh CAN Enable Channel byte 2 ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0 CANGIE C1h CAN General Interrupt Enable – – ENRX ENTX ENERCH ENBUF ENERG – CANIE1 CAN Interrupt C2h Enable Channel byte 1 – IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8 CANIE2 CAN Interrupt C3h Enable Channel byte 2 IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0 CANSIT1 CAN Status BAh Interrupt Channel byte1 – SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 CANSIT2 CAN Status BBh Interrupt Channel byte2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 CANTCON A1h CAN Timer Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 CANTIMH ADh CAN Timer high CANTIM 15 CANTIM 14 CANTIM 13 CANTIM 12 CANTIM 11 CANTIM 10 CANTIM 9 CANTIM 8 CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0 CANSTMH AFh CAN Timer Stamp high TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 TIMSTMP 9 TIMSTMP 8 CANSTML AEh CAN Timer Stamp low TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0 CANTTCH A5h CAN Timer TTC high TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8 CANTTCL A4h CAN Timer TTC low TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 CANTEC 9Ch CAN Transmit Error Counter TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 CANREC 9Dh CAN Receive Error Counter REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 CANPAGE B1h CAN Page CHNB3 CHNB2 CHNB1 CHNB0 AINC INDX2 INDX1 INDX0 CANSTCH B2h CAN Status Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR CANCONH B3h CAN Control Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0 CANMSG A3h CAN Message Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0 4129N–CAN–03/08 11 11 Page

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