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PDF ICS9248-77 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-77 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9248-77
Frequency Timing Generator for PENTIUM II Systems
General Description
The ICS9248-77 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9212-01.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting
to board design iterations or costly shielding. The ICS9248-
77 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
The CPU/2 clocks are inputs to the DRCG.
Features
Generates the following system clocks:
- 3 - CPUs @ 2.5V, up to 150MHz.
- 3 - IOAPIC @ 2.5V, PCI or PCI/2
- 3 - 3V66MHz @ 3.3V.
- 11 - PCIs @ 3.3V.
- 1 - 48MHz, @ 3.3V fixed.
- 1 - 24MHz, @ 3.3V fixed.
- 1 - CPU/2, @ 2.5V.
± .25% center spread, or 0 to -.5% down spread.
Uses external 14.318MHz crystal.
Pin Configuration
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Block Diagram
Key Specification
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
9248-77 Rev C 10/20/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-77
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
5
5 Page 
ICS9248-77
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, One Sigma1
Jitter, Absolute1
VOH1
VOL1
IOH1
IOL1
tr1
tf1
dt1
tsk1
Tjcyc-cyc1
tj1s1
tjabs1
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
2.4
16
0.5
0.5
45
-500
1Guaranteed by design, not 100% tested in production.
TYP MAX UNITS
3.1 V
0.17 0.4 V
-51 -22 mA
41 mA
1.8 2 ns
1.6 2 ns
49 55 %
50 250 ps
299 500 ps
87 150 ps
235 500 ps
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, One Sigma1
Jitter, Absolute1
VOH1
VOL1
IOH1
IOL1
tr1
tf1
dt1
tsk1
Tjcyc-cyc1
tj1s1
tjabs1
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
2.4
16
45
-250
1Guaranteed by design, not 100% tested in production.
TYP
3.1
0.16
-50
42
2
1.74
49
290
290
30
121
MAX
0.4
-22
UNITS
V
V
mA
mA
2 ns
2 ns
55 %
500 ps
500 ps
150 ps
250 ps
11
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| PDF Descargar | [ Datasheet ICS9248-77.PDF ] | |
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