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ICS9248-90 fiches techniques PDF

Integrated Circuit Systems - Frequency Generator & Integrated Buffers

Numéro de référence ICS9248-90
Description Frequency Generator & Integrated Buffers
Fabricant Integrated Circuit Systems 
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ICS9248-90 fiche technique
Integrated
Circuit
Systems, Inc.
ICS9248 - 90
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9248-90 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include two CPU, six PCI and thirteen SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.25% modulation to reduce the EMI.
Serial programming I2C interface allows changing functions,
stop clock programing and Frequency selection. Additionally,
the device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up. It is not recommended to use I/O dual function pin
for the slots (ISA, PIC, CPU, DIMM). The add on card might
have a pull up or pull down.
Features
• 3.3V outputs: SDRAM, PCI, REF, 48/24MHz
• 2.5V outputs: CPU, IOAPIC
• 20 ohm CPU clock output impedance
• 20 ohm PCI clock output impedance
• Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
• No external load cap for CL=18pF crystals
• ±175 ps CPU clock skew
• 250ps (cycle to cycle) CPU jitter
• Smooth frequency switch, with selections from 66.8
to 133 MHz CPU.
• I2C interface for programming
• 3ms power up clock stable time
• Clock duty cycle 45-55%.
• 48 pin 300 mil SSOP package
• 3.3V operation, 5V tolerant inputs (with series R)
• <5ns propagation delay SDRAM from Buffer Input
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF and 24 and
48 MHz clock outputs typically provide better than 0.5V/ns
slew rates into 20pF.
Block Diagram
X1
X2
BUFFER IN
FS(0:3) 4
MODE
CPU_STOP#
PCI_STOP#
SDATA
SCLK
PLL2
XTAL
OSC
/2
STOP
PLL1
Spread
Spectrum
LATCH
POR
4
Control
Logic
Config.
Reg.
STOP
STOP
PCI
CLOCK
DIVDER
STOP
48MHz
24MHz
IOAPIC
2 REF(0:1)
CPUCLK_F
CPUCLK 1
12 SDRAM (0:11)
SDRAM_F
PCICLK (0:4)
5
PCICLKF
9248-90 Rev C 4/19/00
48-Pin SSOP
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
Power Groups
VDDREF = REF (0:1), X1, X2
VDDPCI = PCICLK_F, PCICLK(0:4)
VDDSDR = SDRAM (0:12), supply for PLL core
VDD48 = 24MHz, 48MHz
VDDLIOAPIC = IOAPIC
VDDLCPU = CPUCLK 1, CPUCLK_F
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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