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PDF ICS9248-162 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-162 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248 - 162
Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6
General Description
The ICS9248-162 is the single chip clock solution for various
mobile chipset platforms. It provides all necessary clock signals
for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-162
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Block Diagram
Features
Up to 137MHz frequency support
Spread Spectrum for EMI control
Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
Provides the following system clocks
- 4-CPUs @ 2.5/3.3V, up to 137MHz.
(including CPUCLK_F)
- 9-SDRAMs @3.3V, up to 137MHz
(including SDRAM_F)
- 8-PCI @3.3V, CPU/2 or CPU/3
(including 1 free running PCICLK_F)
- 1-24/48MHz @3.3V
- 1-48MHz @3.3V fixed
- 2-REF @3.3V, 14.318MHz.
Efficient Power management scheme through PCI
and CLK STOP CLOCKS
Spread Spectrum ± .25%, & 0 to -0.5% down spread
X1
X2
BUFFER IN
FS(3:0)
SEL24_48#
CLK_STOP#
PCI_STOP#
CPU2.5_3.3#
SDATA
SCLK
PD#
PLL2
XTAL
OSC
/2
PLL1
Spread
Spectrum
LATCH
POR
Control
Logic
Config.
Reg.
STOP
STOP
PCI
CLOCK
DIVDER
STOP
Pin Configuration
48MHz
24_48MHz
2 REF(1:0)
CPUCLK_F
3 CPUCLK (2:0)
8 SDRAM (7:0)
SDRAM_F
PCICLK (6:0)
7
PCICLK_F
VDDREF
REF0
GNDREF
X1
X2
VDDPCI
*CPU2.5_3.3#/PCICLK_F
*FS3/PCICLK0
GNDPCI
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GNDPCI
PCICLK5
PCICLK6
VDDCOR
PCI_STOP#
*PD#
GND48
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2*
47 VDDLCPU
46 CPUCLK_F
45 CPUCLK0
44 GNDLCPU
43 CPUCLK1
42 CPUCLK2
41 CLK_STOP#
40 GNDSDR
39 SDRAM_F
38 SDRAM0
37 SDRAM1
36 VDDSDR
35 SDRAM2
34 SDRAM3
33 GNDSDR
32 SDRAM4
31 SDRAM5
30 VDDSDR
29 SDRAM6
28 SDRAM7
27 VDD48
26 48MHz/FS0*
25 24_48MHz/FS1*
Power Groups
VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F
VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F
VDD48, GND48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
VDDCOR = PLL CORE
9248-162 Rev A 8/31/00
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248 - 162
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
PWD
1
1
X
1
X
1
X
1
Description
(Reserved)
(Reserved)
(SEL24_48)#
(Reserved)
Latched FS1#
(Reserved)
Latched FS3#
(Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
35
37
38
26
25
48
2
PWD
1
1
1
1
1
1
1
1
Description
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
48MHz (Act/Inact)
24MHz (Act/Inact)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
5 Page 
ICS9248 - 162
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-162. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-162.
3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-162
CLK_STOP# signal. SDRAMs are controlled as shown.
4. All other clocks continue to run undisturbed.
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-162.PDF ] | |
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