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PDF ICS9248-39 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-39 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248 - 39
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9248-39 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include two CPU, six PCI and thirteen SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.5% or ±0.25% modulation to reduce
the EMI. Serial programming I2C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be
stable within 2ms after power-up. It is not recommended to
use I/O dual function pin for the slots (ISA, PIC, CPU,
DIMM). The add on card might have a pull up or pull down.
Features
• 3.3V outputs: SDRAM, PCI, REF, 48/24MHz
• 2.5V outputs: CPU, IOAPIC
• 20 ohm CPU clock output impedance
• 20 ohm PCI clock output impedance
• Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
• No external load cap for CL=18pF crystals
• ±175 ps CPU clock skew
• 250ps (cycle to cycle) CPU jitter
• Smooth frequency switch, with selections from 66.8
to 150 MHz CPU.
• I2C interface for programming
• 3ms power up clock stable time
• Clock duty cycle 45-55%.
• 48 pin 300 mil SSOP package
• 3.3V operation, 5V tolerant inputs (with series R)
• <5ns propagation delay SDRAM from Buffer Input
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into 20pF
loads while maintaining 50±5% duty cycle. The REF and 24
and 48 MHz clock outputs typically provide better than 0.5V/
ns slew rates into 20pF.
Block Diagram
9248-39 Rev F 12/16/99
48-Pin SSOP
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK 1, CPUCLK_F
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
-
43
44
PWD
X
1
1
1
1
1
1
1
Description
Latched FS2#
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK1 (Act/Inact)
CPUCLK_F (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
ICS9248 - 39
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
26
25
-
21,20,18,17
32,31,29,28
38,37,35,34
PWD
1
X
1
1
1
1
1
1
Description
(Reserved)
Latched FS0#
48MHz (Act/Inact)
24 MHz (Act/Inact)
(Reserved)
SDRAM (8:11) (Active/Inactive)
SDRAM (4:7) (Active/Inactive)
SDRAM (0:3) (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
5 Page 
ICS9248 - 39
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
11
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| PDF Descargar | [ Datasheet ICS9248-39.PDF ] | |
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