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PDF ICS9248-56 Data sheet ( Hoja de datos )

Número de pieza ICS9248-56
Descripción Frequency Generator & Integrated Buffers
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICS9248-56 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS9248-56
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9248-56 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-56 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
Block Diagram
Features
• Generates the following system clocks:
- 2CPU(2.5V) up to 100MHz.
- 6 PCI(3.3V) @ 33.3MHz (Includes one free running).
- 1 REF clks (3.3V) at 14.318MHz.
- 1 Fixed clock at 48MHz
- 1 Fixed clock at 48 or 24MHz
• Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
• Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
• Efficient Power management scheme through stop clocks
and power down modes.
• Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
• 28 pin 209mil SSOP and 173mil TSSOP
Pin Configuration
Power Groups
VDD, GND = PLL core
VDDREF, GNDREF = REF(0:1), X1, X2
VDDPCI, GNDPCI = PCICLK_F, PCICLK (0:4)
VDD48, GND48 = 48MHz, 48/24MHz
9248-56 Rev E 12/27/00
28 pin SSOP and TSSOP
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

1 page




ICS9248-56 pdf
ICS9248-56
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-56 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5

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ICS9248-56 arduino
ICS9248-56
4.40 mm. Body, 0.65 mm. pitch TSSOP
(173 mil)
(0.0256 mil)
SY MBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
In Millimeters
COMMON DIMENSIONS
MIN MA X
- 1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE V A RIA TIONS
6.40 BA SIC
4.30
4.50
0.65 BA SIC
0.45
0.75
SEE V A RIA TIONS
0° 8°
- 0.10
In Inches
COMMON DIMENSIONS
MIN MA X
- .047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE V A RIA TIONS
0.252 BA SIC
.169
.177
0.0256 BA SIC
.018
.030
SEE V A RIA TIONS
0° 8°
- .004
V A RIA TIONS
N
28
D mm.
MIN MA X
9.60
9.80
D (inch)
MIN MA X
.378
M O -1 53 J E D E C
D oc . # 1 0-0038
.386
7/ 6/ 00 R ev B
Ordering Information
ICS9248yG-56-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
11 this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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