PDF ICS9248-61 Data sheet ( Hoja de datos )

Número de pieza	ICS9248-61
Descripción	Frequency Generator & Integrated Buffers
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS9248-61 Frequency Timing Generator for Pentium II Systems General Description The ICS9248-61 is the Main clock solution for Notebook designs using the Intel 440BX style chipset. Along with an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system. Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-61 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Block Diagram Features Generates the following system clocks: - 2CPU(2.5V) up to 100MHz. - 7 PCI(3.3V) @ 33.3MHz (Includes one free running). - 2 REF clks Fixed (3.3V) 48MHz at 14.318MHz. Skew characteristics: - CPU CPU<175ps - PCI PCI < 250ps - PCI_E (early) PCI = 2.1ns - CPU(early) PCI = 1.5ns 4ns Supports Spread Spectrum modulation for CPU and PCI clocks, 0.5% down spread Efficient Power management scheme through stop clocks and power down modes. Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal. 28 pin 209mil SSOP. Pin Configuration Power Groups GNDR/C = REFCLK, CORE, Crystal VDDCOR = Core GNDLCPU, VDDCPU = CPU GND48, VDD48 = 48MHz VDDPCI, GNDPCI - PCICLK, PCICLK_F, PCICLK_E 9248-61 Rev B 1/8/99 28 pin SSOP Pentium is a trademark on Intel Corporation. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 1 page ICS9248-61 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-61 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 5 5 Page

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