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PDF ICS9248-131 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-131 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248 - 131
Frequency Generator & Integrated Buffers for Celeron & PII/III™
RecommendedApplication:
ALI - Aladdin V - mobile style chipsets
Output Features:
3 - CPUs @ 2.5/3.3V, up to 100MHz.
3 -AGPCLK @ 3.3V
13 - SDRAM @ 3.3V
6 - PCI @ 3.3V
1 - 48MHz, @ 3.3V fixed.
1 - REF @ 3.3V, 14.318MHz.
Features:
Support power management: CPU, PCI, AGP stop and
Power down Mode from I2C programming.
Spread spectrum for EMI control.
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU CPU: <250ps
AGP PCI: <550ps
CPU(early)-PCI: 1-4ns, Center 2-6ns
Pin Configuration
VDDF
*REF0/CPU2.5_3.3#
GND
X1
X2
VDDPCI
*PCICLK_F/FS1
*PCICLK0/FS2
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDA
BUFFERIN
GND
*CPU_STOP#/SDRAM11
*PCI_STOP#/SDRAM10
VDDSDR
*AGP_STOP#/SDRAM9
*PD#/SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDAGP
47 AGP0
46 AGP1
45 GND
44 CPUCLK0
43 CPUCLK1
42 VDDL
41 CPUCLK2
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDSDR
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDSDR
29 SDRAM6
28 SDRAM7
27 GND
26 48MHz/FS0*
25 AGP_F/MODE*
48-Pin SSOP
Block Diagram
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
PLL2
X1
X2
CPU2.5_3.3#
SDATA
SCLK
FS (2:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
AGP-STOP#
MODE
BUFFERIN
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
PCI
DIVDER
Stop
AGP
DIVDER
Stop
48MHz
REF
3 CPUCLK (2:0)
5 PCICLK (4:0)
PCICLK_F
AGP (1:0)
2
AGP_F
SDRAM (12:0)
13
Functionality
CPU, SDRAM
FS2 FS1 FS0
(MHz)
111
100
110
101
95.25
83.3
100
97
011
010
91.5
96.22
001
66.67
000
60
Note: REF & IOAPIC = 14.318MHz
Power Groups
Analog
Digital
VDDF
VDDA
VDDPCI
VDDSDR
VDDAGP
PCI
(MHz)
33.33
31.75
33.30
32.33
30.50
32.07
33.33
30.00
AGP
(MHz)
66.67
63.50
66.60
64.66
61.00
64.15
66.67
60.00
9248-131 Rev B 7/17/00
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248 - 131
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
25
-
-
-
17
18
20
21
PWD
1
1
1
1
1
1
1
1
Description
AGP_F (Active/Inactive)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
47
-
-
46
2
PWD
1
1
1
1
1
X
1
1
Description
(Reserved)
(Reserved)
(Reserved)
AGP0 (Act/Inact)
(Reserved)
MODE
AGP1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 6: Optional Register for Possible
Furture Requirements
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for futue
applications.
5
5 Page 
ICS9248 - 131
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
11
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| PDF Descargar | [ Datasheet ICS9248-131.PDF ] | |
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