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PDF ICS9248-134 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-134 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9248-134
Frequency Timing Generator for PENTIUM II/III Systems
Recommended Application:
For Intel Camino Style Chipsets
Output Features:
• 3 - CPUs @ 2.5V, up to 180MHz.
• 1 - CPU/2 @ 2.5V.
• 3 - IOAPIC @ 2.5V, PCI or PCI/2
• 3 - 3V66MHz @ 3.3V.
• 11 - PCIs @ 3.3V
• 1 - 48MHz, @ 3.3V fixed
• 1 - 24/48MHz, @ 3.3V
Features:
• Support power management: Power down Mode
from I2C programming.
• Spread spectrum for EMI control
± 0.25% center spread).
• Uses external 14.318MHz crystal
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps)
X1
X2
SEL24_48#
FREQ_APIC
SDATA
SCLK
FS (4:0)
PD#
Block Diagram
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
/2
CPU
DIVDER
/2
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF (1:0)
CPUCLK (2:0)
CPU/2
IOAPIC (2:0)
PCICLK (9:0)
PCICLK_F
3V66 (2:0)
9248-134 Rev A 8/22/00
Pin Configuration
GND
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GND
*FS0/PCICLK_F
*FS1/PCICLK0
VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2
GND
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GND
PCICLK7
PCICLK8
PCICLK9
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDL
47 IOAPIC0
46 IOAPIC1
45 GND
44 IOAPIC2
43 VDDL
42 CPU/2
41 GND
40 CPUCLK0
39 VDDL
38 CPUCLK1
37 CPUCLK2
36 GND
35 VDD66
34 3V66_0
33 3V66_1
32 3V66_2
31 GND66
30 SDATA
29 SCLK
28 VDD48
27 48MHz/FS4*
26 24_48MHz
25 GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Functionality
FS4 FS3 FS2 FS1 FS0 CPU PCI 3V 66 IOAPIC
0 0 0 0 0 103.00 34.33 68.67 17.17
0 0 0 0 1 105.00 35.00 70.00 17.50
0 0 0 1 0 100.45 33.483 66.967 16.742
0 0 0 1 1 100.90 33.63 67.27 16.82
0 0 1 0 0 107.10 35.700 71.400 17.850
0 0 1 0 1 109.00 36.33 72.67 18.17
0 0 1 1 0 112.00 37.34 74.67 18.67
0 0 1 1 1 114.00 28.50 57.00 14.25
0 1 0 0 0 116.00 29.00 58.00 14.50
0 1 0 0 1 118.00 29.50 59.00 14.75
0 1 0 1 0 133.30 33.33 66.65 16.66
0 1 0 1 1 120.00 30.00 60.00 15.00
0 1 1 0 0 122.00 30.50 61.00 15.25
0 1 1 0 1 125.00 31.25 62.50 15.63
0 1 1 1 0 128.21 32.05 64.105 16.026
0 1 1 1 1 130.00 32.50 65.00 16.25
1 0 0 0 0 132.00 33.00 66.00 16.50
1 0 0 0 1 133.90 33.48 66.95 16.74
1 0 0 1 0 138.00 34.50 69.00 17.25
1 0 0 1 1 142.00 35.50 71.00 17.75
1 0 1 0 0 146.00 36.50 73.00 18.25
1 0 1 0 1 150.00 37.50 75.00 18.75
1 0 1 1 0 153.00 38.25 76.50 19.13
1 0 1 1 1 156.00 39.00 78.00 19.50
1 1 0 0 0 159.00 39.75 79.50 19.88
1 1 0 0 1 162.00 40.50 81.00 20.25
1 1 0 1 0 165.00 41.25 82.50 20.63
1 1 0 1 1 168.00 42.00 84.00 21.00
1 1 1 0 0 171.00 42.75 85.50 21.38
1 1 1 0 1 174.00 43.50 87.00 21.75
1 1 1 1 0 177.00 44.25 88.50 22.13
1 1 1 1 1 180.00 45.00 90.00 22.50
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-134
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH VIN = VDD
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL2 VIN = 0 V; Inputs with pull-up resistors
Operating
IDD3.3OP100 CL = 0 pF; Select @ 100 MHz
Supply Current
IDD3.3OP133 CL = 0 pF; Select @ 133 MHz
Input frequency
Input Capacitance1
Fi VDD = 3.3 V;
CIN Logic Inputs
Transition Time1
Settling Time1
Clk Stabilization1
CINX
Ttrans
Ts
TSTAB
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
1Guaranteed by design, not 100% tested in production.
2
VSS-0.3
-5
-200
11
27
VDD+0.3
0.8
0.1 5
2.0
-100
71 160
76 160
14.318 16
5
36 45
3
5
3
V
V
µA
µA
µA
mA
mA
MHz
pF
pF
ms
ms
ms
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating
Supply Current
Power Down
Supply Current
IDD2.5OP100
IDD2.5OP133
IDD2.5PD
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
CL = 0 pF; PWRDWN# = 0
15 75 mA
18 90 mA
272 400 µA
1Guaranteed by design, not 100% tested in production.
5
5 Page 
ICS9248-134
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
11
11 Page | ||
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| PDF Descargar | [ Datasheet ICS9248-134.PDF ] | |
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