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PDF ICS9248-135 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-135 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-135
Frequency Generator & Integrated Buffers for Celeron & PII/III™& K6
Recommended Application:
Motherboard Single chip clock solution for SIS540,
SIS630 Pentium II/III and K6 chipsets.
Output Features:
• 3- CPUs @ 2.5/3.3V, up to 166MHz.
• 10 - SDRAM @ 3.3V, up to 166MHz
including 2 SDRAM_F's
• 7- PCI @3.3V,
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz).
• 2- REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support FS0-FS3 trapping status bit for I2C read back.
• Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I2C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps
• PCI - PCI: < 500ps
• CPU - SDRAM: < 500ps
• CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDREF
*1REF0/FS3
GNDREF
X1
X2
VDDPCI
*PCICLK_F/FS1
*PCICLK1/FS2
PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDD
GND
SDRAM_STOP#
**PD#
VDD
CPU_STOP#
PCI_STOP#
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1
47 VDDLCPU
46 CPUCLK_F
45 CPUCLK1
44 GNDL
43 CPUCLK2
42 VDD
41 SDRAM_F1
40 SDRAM_F0
39 GND
38 SDRAM7
37 SDRAM6
36 VDD
35 SDRAM5
34 SDRAM4
33 GND
32 SDRAM3
31 SDRAM2
30 VDD
29 SDRAM1
28 SDRAM0
27 VDD
26 48MHz/FS0*1
25 24_48MHz/CPU2.5_3.3#*
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
** These inputs have a 120K pullup to VDD.
1 These are double strength.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
CPU2.5_3.3#
SDATA
SCLK
FS[3:0]
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
48MHz
24_48MHz
2 REF[1:0]
2 CPUCLK [2:1]
CPUCLK_F
8 SDRAM [7:0]
SDRAM_F [1:0]
2
PCICLK [6:1]
6
PCICLK_F
Functionality
FS3 FS2
FS1
FS0
CPU
(MHz)
SDRAM
(MHz)
PCICLK
(MHz)
0 0 0 0 66.6 100.0
33.3
00 0
1 100.0
100.0
33.3
0 0 1 0 150.0 100.0
37.5
0 0 1 1 133.3 100.0
33.3
0 1 0 0 66.8 133.6
33.4
0 10
1 100.0
133.3
33.3
0 1 1 0 100.0 150.0
37.5
0 1 1 1 133.3 133.3
33.3
1 0 0 0 66.8
66.8
33.4
10 0
1 97.0
97.0
32.3
1 0 1 0 70.0
105.0
35.0
1 0 1 1 95.0
95.0
31.7
1 1 0 0 95.0
126.7
31.7
110
1 112.0
112.0
37.3
1 1 1 0 97.0
129.3
32.2
1 1 1 1 96.2
96.2
32.1
9248-135 Rev A 1/16/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-135
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
43
45
46
-
PWD
DESCRIPTION
SEL24_48#
1 (48MHz when set to 0)
(24MHz when set to 1)
1 Reserved
1 Reserved
1 Reserved
1 CPUCLK2 (Act/Inact)
1 CPUCLK1 (Act/Inact)
1 CPUCLK0 (Act/Inact)
1 Reserved
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
14
13
12
11
9
8
7
PWD
DESCRIPTION
1 (CPU2.5_3.3#)
1 PCICLK6 (Act/Inact)
1 PCICLK5 (Act/Inact)
1 PCICLK4 (Act/Inact)
1 PCICLK3 (Act/Inact)
1 PCICLK2 (Act/Inact)
1 PCICLK1 (Act/Inact)
1 PCICLK_F (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
32
31
29
28
-
-
-
-
PWD
DESCRIPTION
1 SDRAM3 (Act/Inact)
1 SDRAM2 (Act/Inact)
1 SDRAM1 (Act/Inact)
1 SDRAM0 (Act/Inact)
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
25
26
41
40
38
37
35
34
PWD
DESCRIPTION
1 24_48MHz
1 48MHz
1 SDRAM_F1
1 SDRAM_F0
1 SDRAM7
1 SDRAM6
1 SDRAM5
1 SDRAM4
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
48
2
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 FS3#
1 FS2#
1 FS1#
1 FS0#
1 REF1 (Act/Inact)
1 REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this register
can cause malfunction
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-135
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
Input Low Voltage
Operating
Supply Current
Input frequency
Input Capacitance1
Transition Time1
Clk Stabilization1
VIH
VIL
IDD3.3OP66
IDD3.3OP100
IDD3.3OP133
Fi
CIN
CINX
Ttrans
TSTAB
CL = 0 pF; Select @ 66MHz
CL = 0 pF; Select @ 100MHz
CL = 0 pF; Select @ 133MHz
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
2
VSS-0.3
11
27
VDD+0.3
0.8
148 180
150 180
161
14.318 16
5
36 45
3
3
V
V
mA
mA
mA
MHz
pF
pF
ms
ms
Skew
tCPU-PCI VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
1 2.39 4
ns
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating Supply
Current
Skew1
IDD2.5OP66
IDD2.5OP100
IDD2.5OP133
tCPU-SDRAM
tCPU-PCI
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
VT = 1.5 V; VTL = 1.25 V
VT = 1.5 V; VTL = 1.25 V
6.13 30 mA
9.22 mA
11.6 mA
273 500
ps
1 2.25 4
ns
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-135.PDF ] | |
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