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PDF ICS9248-136 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-136 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9248-136
Advance Information
Frequency Generator & Integrated Buffers for K7 Processor
Recommended Application:
Single chip clock solution for SIS 730S K7 chipset.
Output Features:
• 1 - Differential pair open drain CPU clock
• 1 - Single-ended open drain CPU clock
• 13 - SDRAM @ 3.3V
• 6- PCI @3.3V,
• 2 - AGP @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 2- REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support FS0-FS3 trapping status bit for I2C read back.
• Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I2C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps
• PCI - PCI: < 500ps
• CPU - SDRAM: < 500ps
• CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
1*(AGPSEL)REF1
1*(FS3)REF0
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDCPU
47 CPUCLKT0
46 CPUCLKC0
45 CPUCLKT1
44 GND
43 VDDSDR
42 SDRAM0
41 SDRAM1
40 SDRAM2
39 GND
38 SDRAM3
37 SDRAM4
36 SDRAM5
35 VDDSDR
34 SDRAM6
33 SDRAM7
32 GND
31 SDRAM8/PD#
30 SDRAM9/SDRAM_STOP#
29 GND
28 SDRAM10/PCI_STOP#
27 SDRAM11/CPU_STOP#
26 SDRAM12
25 VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
AGP
DIVDER
Functionality
48MHz
24_48MHz
REF (1:0)
2
CPUCLKC0
CPUCLKT (1:0)
2
SDRAM (12:0)
13
PCICLK (4:0)
5
PCICLK_F
AGP (1:0)
2
FS3 FS2 FS1 FS0 CPU SDRAM
0 0 0 0 100.00 100.00
0 0 0 1 100.00 133.33
0 0 1 0 100.00 150.00
0 0 1 1 100.00 66.67
0 1 0 0 112.00 112.00
0 1 0 1 125.00 100.00
0 1 1 0 124.00 124.00
0 1 1 1 133.33 100.00
1 0 0 0 133.33 133.33
1 0 0 1 150.00 150.00
1 0 1 0 111.11 166.67
1 0 1 1 110.00 165.00
1 1 0 0 166.67 166.67
1 1 0 1 90.00 90.00
1 1 1 0 48.00 48.00
1 1 1 1 45.00 60.00
P CICLK
33.33
33.33
30.00
33.33
33.60
31.25
31.00
33.33
33.33
30.00
33.33
33.00
33.33
30.00
32.00
30.00
AGP
SEL = 0
66.67
66.67
60.00
66.67
67.20
62.50
62.00
66.67
66.67
60.00
66.67
66.00
66.67
60.00
64.00
60.00
AGP
SEL = 1
50.00
50.00
50.00
50.00
56.00
50.00
46.50
50.00
50.00
50.00
55.56
55.00
55.56
45.00
48.00
45.00
9248-136 Rev - 03/29/01
Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
1 page  
ICS9248-136
Advance Information
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
47
46
45
-
PWD
DESCRIPTION
1
Sel24_48
(1:24MHz, 0:48MHz)
1 Reserved
1 Reserved
1 Reserved
1 CPUCLKT0
1 CPUCLKC0
1 CPUCLKT1
1 Reserved
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
13
12
11
10
9
8
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reserved
Reserved
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
33
34
36
37
38
40
41
42
PWD
DESCRIPTION
1 SDRAM7
1 SDRAM6
1 SDRAM5
1 SDRAM4
1 SDRAM3
1 SDRAM2
1 SDRAM1
1 SDRAM0
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
21
20
26
27
28
30
31
PWD
DESCRIPTION
1 Reserved
1 24_48MHz
1 48MHz
1 SDRAM12
1 SDRAM11
1 SDRAM10
1 SDRAM9
1 SDRAM8
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
3
2
17
16
PWD
DESCRIPTION
X FS3 (Readback)
X FS2 (Readback)
X FS1 (Readback)
X FS0 (Readback)
1 REF1
1 REF0
1 AGPCLK1
1 AGPCLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-136
Advance Information
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248-
136 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-136.PDF ] | |
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