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PDF ICS9248-110 Data sheet ( Hoja de datos )
| Número de pieza | ICS9248-110 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9248-110
AMD-K7TM System Clock Chip
Recommended Application:
AMD-K7 based systems
Output Features:
• 3 differential pair open drain CPU clocks (2.7V external
pull-up; up to 150MHz achieviable through I2C)
• 2 - AGPCLK @ 3.3V
• 8 - PCI @3.3V, including 1 free running
• 1 - 48MHz @ 3.3V
• 1 - 24/48MHz @ 3.3V
• 2- REF @3.3V, 14.318MHz.
Features:
• Up to 150MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode from I2C programming.
• Spread spectrum for EMI control -0.5% down spread
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU – CPU: <250ps
• AGP-AGP: <250ps
• PCI – PCI: <400ps
• CPU - SDRAM_OUT: <400ps
• CPU-AGP <250ps
Pin Configuration
**FS0/REF0
**FS1/REF1
GNDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK0
VDDPCI
PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
VDDAGP
AGP0
AGP1
GNDAGP
VDD48
48MHz
SEL24_48#/24-48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDREF
47 GNDSD
46 SDRAM_OUT
45 VDDSD
44 RESERVED
43 CPUCLKC2
42 CPUCLKT2
41 GNDCPU
40 CUCLKC1
39 CPUCLKT1
38 GND
37 CPUCLKC0
36 CPUCLKT0
35 RESERVED
34 VDD
33 GND
32 PCI_STOP#
31 CPU_STOP
30 PD#
29 SPREAD#
28 FS2*
27 SDATA
26 SCLK
25 GND48
48-Pin 300mil SSOP
* Internal 120K pullup resistor on indicated inputs
** Internal 240K pullup resistor on indicated inputs
Block Diagram
X1
X2
CPU_STOP#
FS (2:0)
SPREAD#
PD#
PCI_STOP#
OSC
PLL CPU
STOP
/2 /3
X2
PCI
STOP
SEL24_48#
PLL2
/2
REF (1:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
SDRAM_OUT
AGP (1:0)
PCICLK (6:0)
PCICLK_F
48MHz
24_48MHz
Functionality
FS2 FS1 FS0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CPU,
SDRAM
90
95
100.99
115
100.7
103
105
110
PCI
30.00
31.67
33.66
38.33
33.57
34.33
35.00
36.67
AGP
60.00
63.33
67.33
76.67
67.13
68.67
70.00
73.33
9248-110 Rev C 01/08/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9248-110
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-110 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9248-110
Electrical Characteristics - USB, REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
RDSP2B1 VO=VDD*(0.5)
Output Impedance
RDSN2B1 VO=VDD*(0.5)
Output High Voltage
VOH5 IOH = -12 mA
Output Low Voltage
VOL5
IOL = 9 mA
Output High Current
IOH5 VOH = 2.0 V
Output Low Current
IOL5 VOL = 0.8 V
Rise Time1
tr51 VOL = 0.4 V, VOH = 2.4 V
Fall Time1
tf51 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle1
dt51 VT = 1.5 V
REF Jitter, Cyl-to-Cyl
tjcyc-cyc51 VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
20 47 60 Ω
20 44 60 Ω
2.4 V
0.4 V
-22 mA
16 mA
2.6 4.0 ns
2.5 4.0 ns
45 51 55 %
320 700 ps
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time1
Fall Time1
Differential voltage-AC1
Differential voltage-DC1
Diff Crossover Voltage1
Duty Cycle1
Skew window1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
ZO1
VOH2B
VOL2B
IOL2B
tr2B1
tf2B1
VDIF
VDIF
VX
dt2B1
tsk2B1
tjcyc-cyc2B1
tjabs2B1
VO=VX
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
VOL = 20% , VOH = 80%
VOH = 80%, VOL = 20%
Note 2
Note 2
Note 3
VT = 50%
VT = 50%
VT = VX
VT = 50%
60 Ω
1 1.8 V
0.8 V
18 mA
2.4 2.6 ns
1.2 2.6 ns
0.4 Vpull-up(ext) V
0.2 Vpull-up(ext) V
1.1 1.4 1.7 V
44 46 54 %
40 200 ps
80 250 ps
120 250 ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the
"true" input Level and VCP is the "complement" input level.
3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS9248-110.PDF ] | |
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