PDF ADV7400A Data sheet ( Hoja de datos )

Número de pieza	ADV7400A
Descripción	10-Bit Integrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
Fabricantes	Analog Devices
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No Preview Available ! 10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer ADV7400A FEATURES Three 10-bit ADCs sampling up to 110 MHz 12 analog input channel mux NTSC/PAL/SECAM color standards support Adaptive digital line length tracking (ADLLT™), signal processing, and enhanced FIFO management give mini TBC functionality 525p/625p component progressive scan support 720p/1080i component HDTV support Digitizes RGB graphics up to 1280 × 1024 @ 60 Hz (SXGA) 24-bit digital input port supports data from DVI/HDMI Rx IC Any-to-any 3 × 3 color-space conversion matrix Industrial temperature range (−40°C to +85°C) 12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface Programmable interrupt request output pin APPLICATIONS LCD/DLP™ rear projection HDTVs PDP HDTVs CRT HDTVs LCD/DLP front projectors LCD TV (HDTV-ready) HDTV STBs with PVR Hard disk-based video recorders Multiformat scan converters DVD recorders with progressive scan input support GENERAL DESCRIPTION The ADV7400A is a high quality, single chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-video into a digital ITU-R BT.656 format. The ADV7400A also supports decoding a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other HD and SMPTE standards. Graphic digitization is also supported by the ADV7400A; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. The ADV7400A contains two main processing sections. The first is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. For more specific descriptions of the ADV7400A features, see the Detailed Functionality and Detailed Description sections. FUNCTIONAL BLOCK DIAGRAM ANALOG INTERFACE RGB YPrPb YC AND CVBS SOG SOY HS_IN/ CS_IN VS_IN 12-CH INPUT MATRIX CLAMP CLAMP CLAMP SYNC PROCESSING & CLOCK GENERATION 10 A/D 10 A/D 10 A/D HS/CS & VS CONTROL CONTROL SCLK1 SDA1 SCLK2 SDA2 ALSB DUAL PORT SERIAL INTERFACE CONTROL (1) & VBI DATA (2) CONTROL & DATA CONTROL SERIAL INTERFACE DCLK_IN DE_IN HS_IN/ CS_IN VS_IN DIGITAL VIDEO INPUT PORT 24 SYNC/CONTROL DATA PREPROCESSOR (A) SYNC (B) COLOR SPACE (C) CONVERTER DECIMATION AND DOWN- SAMPLING FILTERS (A) (B) (C) DIGITAL PROCESSING BLOCK COMPONENT PROCESSOR SYNC SOURCE & POLARITY DETECT SYNC EXTRACTION MACROVISION® & CGMS DETECTION STANDARD IDENTIFICATION AV CODE INSERTION TIMING CONTROL DIGITAL FINE CLAMP GAIN & OFFSET CONTROL NOISE & CALIBRATION MEASUREMENT STANDARD DEFINITION PROCESSOR LUMA FILTERING DIGITAL CLAMP & GAIN CONTROL LUMA RESAMPLER 2D 4H COMB FILTER ADAPTIVE SYNC EXTRACTION (ADLLT) RESAMPLE AV CODE CONTROL INSERTION CHROMA FILTERING & DEMODULATION DIGITAL CLAMP & GAIN CONTROL CHROMA RESAMPLER CTI 2D 4H COMB FILTER 8 8 PIXEL DATA 8 HS VS FIELD/DE LLC1 SFL/ SYNC_OUT INT 10 24 CVBS DVI/HDMI DIGITAL INTERFACE GLOBAL CONTROL & VBI DATA SLICER MACROVISION DETECTION Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 1 page ADV7400A TIMING CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise noted. Table 3. Timing Characteristics1, 2, 3 Parameter Symbol Test Conditions Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency 27.0 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC1 Frequency Range4 12.825 110 MHz I2C® PORT SCLK Frequency 400 kHz SCLK Min Pulse Width High t1 0.6 µs SCLK Min Pulse Width Low t2 1.3 µs Hold Time (Start Condition) t3 0.6 µs Setup Time (Start Condition) t4 0.6 µs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 µs RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio t9:t10 45:55 55:45 % duty cycle DATA and CONTROL OUTPUTS Data Output Transition Time (SDP) t11 Negative clock edge to start of valid data 3.4 ns Data Output Transition Time (SDP) t12 End of valid data to negative clock edge 2.4 ns Data Output Transition Time (CP) t13 End of valid data to negative clock edge 1.1 ns Data Output Transition Time (CP) Data Output Transition Time DDR (CP)5 Data Output Transition Time DDR (CP)5 Data Output Transition Time DDR (CP)5 Data Output Transition Time DDR (CP)5 t14 t15 t16 t17 t18 Negative clock edge to start of valid edge Positive clock edge to end of valid data Start of valid data to positive clock edge Negative clock edge to end of valid data Start of valid data to negative clock edge −2.7 + TLLC1/4 −1.3 + TLLC1/4 −2.1 + TLLC1/4 −0.9 + TLLC1/4 2.2 ns ns ns ns ns DATA and CONTROL INPUTS Input Setup Time t19 HS_IN, VS_IN 9 ns DE_IN, data inputs 2.2 ns Input Hold Time t20 HS_IN, VS_IN 7 ns DE_IN, data inputs 1 ns 1 The min/max specifications are guaranteed over this range. 2 Temperature range TMIN to TMAX: −40°C to +85°C. 3 Guaranteed by characterization. 4 Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80. 5 DDR timing specifications depend on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz. Rev. A \| Page 5 of 16 5 Page • Free-run output mode provides stable timing when no video input is present • Arbitrary pixel sampling support for nonstandard video sources RGB GRAPHICS PROCESSING • 110 MSPS conversion rate supports RGB input resolutions up to 1280 × 1024 @ 60 Hz (SXGA); (80 MSPS conversion rate for ADV7400AKSTZ-80) • Automatic or manual clamp and gain controls for graphics modes • Contrast and brightness controls • Sampling PLL clock with 500 ps p-p jitter at 110 MSPS • 32-phase DLL allows optimum pixel clock sampling • Automatic detection of sync source and polarity by SSPD block • Standard identification is enabled by STDI block • RGB can be color space converted to YCrCb and decimated to a 4:2:2 format for video centric backend IC interfacing • Data enable (DE) output signal supplied for direct connection to HDMI/DVI Tx IC • Arbitrary pixel sampling support for nonstandard video sources ADV7400A DIGITAL VIDEO INPUT PORT • Support for raw 10-bit CVBS data from digital tuner • Support for 24-bit RGB input data from DVI Rx chip, output converted to YCrCb 4:2:2 • Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, VGA to SXGA @ 60 Hz input data from HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb GENERAL FEATURES • HS, VS, and FIELD output signals with programmable position, polarity, and width • Programmable interrupt request output pin, INT, signals SDP/CP status changes • Supports two I2C host port interfaces (control and VBI) • Low power consumption: 1.8 V digital core, 3.3 V analog and digital I/O, low power power-down mode, and green PC mode • Industrial temperature range (−40°C to +85°C) • 110 MHz and 80 MHz speed grades (ADV7400AKSTZ- 110 and ADV7400AKSTZ-80) • 100-pin 14 mm × 14 mm Pb-free LQFP package Rev. A \| Page 11 of 16 11 Page

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