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PDF KS57P21132 Data sheet ( Hoja de datos )
| Número de pieza | KS57P21132 | |
| Descripción | (KS57C21116 - KS57P21132) single-chip CMOS microcontroller | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KS57P21132 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
1 PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance
using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-1280-dot LCD direct drive capability, segment expandable circuit, 8-bit and 16-bit timer/counter,
and serial I/O, the KS57C21116/C21124/C21132 offers an excellent design solution for a wide variety of
applications which require LCD functions.
Up to 51 pins of the 128-pin QFP package can be dedicated to I/O. Nine vectored interrupts provide fast
response to internal and external events. In addition, the KS57C21116/C21124/C21132's advanced CMOS
technology provides for low power consumption and a wide operating voltage range.
OTP
The KS57C21116/C21124/C21132 microcontroller is also available in OTP (One Time Programmable) version,
KS57P21132. KS57P21132 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of
masked ROM. The KS57P21132 is comparable to KS57C21116/C21124/C21132, both in function and in pin
configuration except ROM size.
1-1
1 page  
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C SC2 SC1 SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, ….., or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a Crystal, Ceramic, or RC oscillation source, or an externally-
generated clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU
clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided inter-
nally to produce four CPU clock frequencies — fx/4, fx/8, fx/64, or fxt/4.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, INT4, and INTK). There are two quasi-interrupts: INT2 and INTW.
INT2 detects rising or falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91
milliseconds. The following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1-5
5 Page 
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
Table 1-1. KS57C21116/C21124/C21132 Pin Descriptions (Continued)
Pin Name
INT0
INT1
INT2
INT4
M
LCDFR
CLO1
CLO2
CL
TCLO0
TCLO1
TCL0
TCL1
CIN0–CIN2
SEG0–SEG47
SEG48–
SEG79
SEG80–
SEG87
COM0–COM7
COM8–COM15
Pin Type
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
Description
External interrupts with rising/falling edge detection
External interrupts with rising/falling edge detection
External quasi-interrupts with rising/falling edge
detection
External interrupts with rising/falling edge detection
Alternated signal for SEG driver
Synchronous frame signal for SEG driver
Clock output or operating clock for SEG driver
Clock output or operating clock for SEG driver
Data shift clock for SEG driver
Timer/counter0 clock output
Timer/counter1 clock output
External clock input for timer/counter 0
External clock input for timer/counter 1
CIN0,1: comparator input only
CIN2: comparator input or external reference input
LCD segment data output
LCD segment data output
LCD segment data output
LCD common data output
LCD common data output
VLC1–VLC5
VDD
VSS
Xin, Xout
XTin, XTout
TEST
RESET
– LCD power supply. Voltage dividing resistors are
fixed.
– Main power supply
– Ground
– Crystal, Ceramic, or RC oscillator signal I/O for main
system clock.
– Crystal oscillator signal I/O for subsystem clock.
I Test signal input (must be connected to VSS)
I Reset signal
Number
28
29
30
31
32
33
34
35
36
36
37
38
39
40, 41
42
122–75
74–43
2,1,
128–123
10–3
123–128
1, 2
15–11
20
21
23, 22
25, 26
24
27
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
Share Pin
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.0
P3.1
P3.2
P3.3
P4.0–P4.1
P4.2
–
Port13–6
COM15–8
–
SEG87–80
–
–
–
–
–
–
–
1-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KS57P21132.PDF ] | |
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