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PDF 74LVTH16240 Data sheet ( Hoja de datos )
| Número de pieza | 74LVTH16240 | |
| Descripción | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1999
Revised March 1999
74LVT16240 • 74LVTH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16240 and LVTH16240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus-oriented
transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16240 and
LVTH16240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16240), also
available without bushold feature (74LVT16240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 16240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS012025.prf
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74LVTH16240.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74LVTH16240 | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | Fairchild Semiconductor |
| 74LVTH16240MEA | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | Fairchild Semiconductor |
| 74LVTH16240MTD | Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs | Fairchild Semiconductor |
| 74LVTH16244 | Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs | Fairchild Semiconductor |
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