M36LLR8760 Datasheet PDF - ST Microelectronics
| Part Number | M36LLR8760 | |
| Description | 256 + 128 Mbit (Multiple Bank / Multi-Level / Burst) Flash Memory 64 Mbit (Burst) PSRAM | |
| Manufacturers | ST Microelectronics | |
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M36LLR8760T1, M36LLR8760D1
M36LLR8760M1, M36LLR8760B1
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
TARGET SPECIFICATION
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
– 1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-Level, Burst) Flash Memory
– 1 die of 64 Mbit (4Mb x16) Pseudo SRAM
■ SUPPLY VOLTAGE
– VDDF1 = VDDF2 = VCCP = VDDQF = 1.7 to
1.95V
– VPPF = 9V for fast program (12V tolerant)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Configuration (Top + Top)
M36LLR8760T1: 880Dh + 88C4h
– Mixed Configuration (Bottom + Top)
M36LLR8760D1: 880Eh + 88C4h
– Mixed Configuration (Top + Bottom)
M36LLR8760M1: 880Dh + 88C5h
– Bottom Configuration (Bottom + Bottom)
M36LLR8760B1: 880Eh + 88C5h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORIES
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
■ SYNCHRONOUS BURST READ SUSPEND
■ PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
■ MEMORY ORGANIZATION
– Multiple Bank Memory Array:
16 Mbit Banks for the 256 Mbit Memory
8 Mbit Banks for the 128 Mbit Memory
– Parameter Blocks (at Top or Bottom)
Figure 1. Package
FBGA
LFBGA88 (ZAQ)
8 x 10mm
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
PSRAM
■ ACCESS TIME: 70ns
■ ASYNCHRONOUS PAGE READ
– Page Size: 16 words
– Subsequent read within page: 20ns
■ LOW POWER FEATURES
– Temperature Compensated Refresh
(TCR)
– Partial Array Refresh (PAR)
– Deep Power-Down (DPD) Mode
■ SYNCHRONOUS BURST READ/WRITE
July 2005
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
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M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 2. Logic Diagram
VDDQF VPPF
VDDF1 VDDF2 VCCP
24
A0-A23
16
EF1
GF1
EF2
GF2
WF
RPF
WPF
L
K
EP
DQ0-DQ15
M36LLR8760T1
M36LLR8760D1
M36LLR8760M1
M36LLR8760B1
WAIT
GP
WP
CRP
UBP
LBP
VSS
AI10908b
Table 1. Signal Names
A0-A23(1) Address Inputs
DQ0-DQ15 Common Data Input/Output
L
Common Flash and PSRAM Latch
Enable Input
K Common Flash and PSRAM Burst Clock
WAIT
Wait Data in Burst Mode for both Flash
memories and PSRAM
VDDF1
Flash 1 Power Supply
VDDF2
Flash 2 Power Supply
VDDQF
Common Flash Supply for I/O Buffers
VPPF
Common Flash Optional Supply Voltage
for Fast Program & Erase
VSS Common, Ground
VCCP
PSRAM Power Supply
NC Not Connected Internally
DU Do Not Use as Internally Connected
Flash Memory Signals
EF1 Flash 1 Chip Enable Input
GF1 Flash 1 Output Enable Input
EF2 Flash 2 Chip Enable Input
GF2 Flash 2 Output Enable Input
WF
Common Flash Memory Write Enable
Input
RPF Common Flash Memory Reset input
WPF
Common Flash Memory Write Protect
Input
PSRAM Signals
EP Chip Enable Input
GP Output Enable Input
WP Write Enable Input
CRP
Configuration Register Enable Input
UBP
Upper Byte Enable Input
LBP Lower Byte Enable Input
Note: 1. A22 is an Address Input for the two Flash memories only.
A23 is for the 256Mb Flash memory component only.
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| Information | Total 19 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ M36LLR8760.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
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