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PDF TC9205M Data sheet ( Hoja de datos )
| Número de pieza | TC9205M | |
| Descripción | 5-Port 10/100/1000 Smart Ethernet Switch | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC9205M (archivo pdf) en la parte inferior de esta página. Total 51 Páginas | ||
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TC9205M
Preliminary Data Sheet
5-Port 10/100/1000 Smart Ethernet Switch
Features
Stand Alone Switch On A Chip
5 Ethernet 10/100/1000 ports
I Ethernet 10/100 port
MII/GMII interface for 5 ports
I extra MII interface for 6th port
Four Classes of Service (CoS) selectable for
each port and/or checked via IP Header and
802.1Q VLAN Tag
Five port-based VLANs
Maximum throughput, non head-of-line
blocking architecture
Embedded SSRAM packet buffer/address table
8K MAC address table
Each port is configurable to 10 full/half duplex,
100 full/half duplex and 1000 full duplex mode
Flow-control ability is able to set for both full
and half duplex mode
Broadcast throttling
Port Mirroring
Serial EEPROM Interface, EEPROM is optional
MDIO master for PHY configuration / polling
0.18 micron technology
2V and 3.3V dual voltage power supply
Packaged in PBGA 292
25MHz crystal input only
General Description
TC9205M is a fully integrated 5 Port 10/100/1000
smart Ethernet switch controller designed for low
cost and high performance solutions. The chip
embeds necessary SSRAM for packet buffering
and MAC address table. It provides MII / GMII /
interface for all ports.
A store-and-forward switching method using a
non-blocking architecture is implemented within
TC9205M to improve the availability and
bandwidth. The chip embeds packet buffer, which
it supports normal and priority queues for each
transmission port.
TC9205M provides evolved CoS with four levels
of priority. The priority can be checked via layer 2
(802.1Q VLAN Tagging) and/or layer 3 (IP Header
TOS bits) packets. Port based priority is also
provided to ensure transmission with precedence
for all packets incoming from selected port(s).
This feature allows improved support for
multimedia applications.
The chip embeds IEEE 802.3 MAC functions for
each port and these functions support full and half
duplex modes for both 10 and 100 Mbits/s data
rates and full duplex for 1000 Mbit/s. Each port
includes dedicated receive and transmit FIFOs
with necessary logic to implement flow control for
both full and half duplex modes. TC9205M uses
IEEE 802.3x frame based flow control for full
duplex and backpressure for half duplex.
TC9205M handles an 8K address-lookup table
with searching, self-learning, and automatic aging,
at very high speed and excellent address space
coverage. Forwarding rules are implemented
according to IEEE 802.1D specifications. Filtering
capabilities for bad packets and packets with
Reserved Group Address DA are also provided.
The pin configuration interface comprises 40
configurations, which are shared with GMII output
pins by latching the configuration data during
reset. An external EEPROM device can also be
used to configure the TC9205M at power-up. With
reference to pin configuration interface, the
EEPROM extends the chip’s configuration
capability with new features and enables a
jumper-less configuration mode using a parallel
interface for reprogramming. A virtual internal
EEPROM mode is also provided to enable the
use of the programming interface in the absence
of external EEPROM. TC9205M can make
effective use by most of its features using only the
pin configuration interface.
TC9205M includes a physical layer configuration /
polling entity, which it is use to configure the phy
functions and to monitor the physical layer
transceiver’s speed, duplex mode, link status and
full duplex flow control ability for each port. The
chip provides four modes for phy configurations,
which these modes include auto-negotiation
disable procedure for 10/100 speed modes. The
phy configuration information is stored in
EEPROM setting.
The chip requires a 25 MHz system clock, dual 2V
and 3.3V power supply and is packaged in PBGA
292.
Confidential.
Copyright © 2003, IC Plus Corp.
1/51
July 30, 2003
TC9205M-DS-R03
1 page  
TC9205M
Preliminary Data Sheet
Pins Placement
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A RXD00
CRS0
COL0
A
B
RXD03
RXD02
RXD01
VSS3.3
VSS3.3 VSS3.3
B
C
RXD06
RXD05
RXD04
TXER7
VSS3.3
TESTINT SDA
C
D
RXDV0
RXD07 RXCLK0 RXER0
E TXD00 TXCLK0 GTXCLK0 VSS3.3
VSS2.0 VDD3.3 VDD2.0 VSS2.0 VSS3.3 VSS3.3 VSS2.0 VDD2.0 VDD3.3 VSS3.3 VSS3.3 VSS2.0
SCL
MDIO
DMDC
TXER5
TXEN5
FullBp
ECarrBp
F TXD03 TXD02 TXD01 VSS3.3
VSS2.0 DisBkPr
FTXD53
G TXD06
TXD05
TXD04
VDD3.3
VDD3.3
TXD50
TXD51
GTXD52
H TXER0
TXEN0
TXD07
VDD2.0
GND
GND
GND
GND
GND
GND
VDD2.0
TXCLK5 RXER5
RXDV5
H
J RXD10
CRS1
COL1 VDD3.3
K
RXD13
RXD12
RXD11
VSS2.0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RXCLK5
VDD3.3
J
KRXD53
L RXD17 RXD16 RXD15 RXD14
GND
GND
GND
GND
GND
GND
VSS3.3
RXD52
RXD51
RXD50
L
M
RXDV1
RXCLK1 GTXCLK1 VDD3.3
GND
GND
GND
GND
GND
GND
VDD3.3 TXEN4 COL5
MCRS5
N RXER1 TXCLK1
TXD10
VDD2.0
GND
GND
GND
GND
GND
GND
VDD2.0
TXD46
TXD47
NTXER4
P TXD11
TXD12
TXD13
VDD3.3
VDD3.3
TXD43
TXD44
PTXD45
R TXD16
TXD15
TXD14
VSS3.3
VSS2.0
TXD40
TXD41
RTXD42
T TXD17 TXER1 TXEN1 VSS2.0
RXCLK4
RXDV4 GTXCLK4 TXCLK4
T
U GTXCK RESET
SYSCK SELSCK VSS3.3 VSS3.3 VDD3.3 VDD2.0 VDD3.3 VSS3.3 VSS3.3 VDD3.3 VDD2.0 VDD3.3 VSS3.3 VSS2.0
RXD45
RXD46
RXD47
URXER4
V VDD18PLL
BCSTLED
OVUNLED
RXD24
W CRS2
RXD20
COL2
RXD25
RXD27 RXCLK2 TXD22
RXDV2 GTXCLK2 TXD21
TXD23
TXD24
TXEN2
TXD27
COL3
CRS3
RXD30 RXD35 RXD36 RXCLK3 TXD31
RXD31 RXD34 RXD37 TXCLK3 TXD30
TXD32 TXD35
COL4
CRS4
VRXD44
TXD33
TXD36
TXEN3
RXD40
WRXD43
Y RXD21
RXD22
RXD23
RXD26
RXER2 TXCLK2 TXD20
TXD25
TXD26
TXER2
RXD32
RXD33
RXDV3 GTXCLK3 RXER3
TXD34
TXD37
TXER3
RXD41
YRXD42
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Top View
Confidential.
Copyright © 2003, IC Plus Corp.
5/51
July 30, 2003
TC9205M-DS-R03
5 Page 
TC9205M
Preliminary Data Sheet
Pin Listing (continued)
No.
W18
Y14
D15
Y18
W14
W10
V10
Y15
H17
V14
Y13
V11
Pin label
TxEn3
GTxClk3
Vss 3.3
TxEr3
TxClk3
Crs3
Col3
RxEr3
Vdd 2.0
RxClk3
RxDv3
RxData3_0
W11 RxData3_1
Y11 RxData3_2
Y12 RxData3_3
W12
V12
V13
W13
N19
RxData3_4
RxData3_5
RxData3_6
RxData3_7
TxData4_7
BcstThrot
N18 TxData4_6
OBMTest
P20 TxData4_5
FcBcstMode
Type
O
O
G
I/Opd
I
Is
Is
Is
P
I
Is
Is
Is
Is
Is
Is
Is
Is
Is
I/Opd
I/Opd
I/Opd
Description
GMII/MII transmit enable
GMII transmit clock
Digital ground for I/O
Transmit Error
MII transmit clock
MII carrier sense indication
MII collision indication
Receive Error
Digital +2.0V power supply for core
MII receive clock
GMII/MII data valid
GMII receive data - least significant nibble.
MII receive data
GMII receive data - least significant nibble.
MII receive data
GMII receive data - least significant nibble.
MII receive data
GMII receive data - least significant nibble.
MII receive data
GMII receive data - most significant nibble
GMII receive data - most significant nibble
GMII receive data - most significant nibble
GMII receive data - most significant nibble
GMII transmit data - bit 7
Enables broadcast throttling.
'1' – Enable
'0' – Disable
BcstThrot is latched on reset.
GMII transmit data - bit 6
Sets the switch into a special test mode. This test mode require
crossover loopbacks cables to be placed on the pair ports: 1 & 2,2 &
3, 3 & 4, 4 & 5,5 & 6 while ports 0 and 7 will be accessible to the test
machine.
'1' – enabled
'0' – disabled
OBMTest is latched on reset.
GMII transmit data - bit 5
Changes the way flow control threshold is handled while in broadcast
situations.
'1' – only the flow control threshold on the broadcast queue is considered
'0' – flow control thresholds associated to each source port originating
the broadcast frames are considered
FCBcstMode is latched on reset.
Confidential.
Copyright © 2003, IC Plus Corp.
11/51
July 30, 2003
TC9205M-DS-R03
11 Page | ||
| Páginas | Total 51 Páginas | |
| PDF Descargar | [ Datasheet TC9205M.PDF ] | |
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