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PDF 29F4000 Data sheet ( Hoja de datos )
| Número de pieza | 29F4000 | |
| Descripción | MX29F4000 | |
| Fabricantes | Macronix | |
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MX29F4000
4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY
FEATURES
• 524,288 x 8 only
• Single power supply operation
- 5.0V only operation for read, erase and program
operation
• Fast access time: 55/70/90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
www.DataSheet4U-.c1oumA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase
8 equal sectors of 64K-Byte each
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Sector protect/unprotect for 5V only system or 5V/
12V system.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 32-pin PDIP
• Pin out compatibe with EPROM standard and software
compatible with single-power supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX29F4000 is a 4-mega bit Flash memory organized
as 512K bytes of 8 bits. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX29F4000 is packaged
in 32-pin PDIP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29F4000 offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F4000 has separate chip enable (CE) and output
enable (OE ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F4000 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F4000 uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to
100 milliamps on address and data pin from -1V to
VCC + 1V.
P/N:PM0629
REV. 1.0, DEC. 20, 1999
1
1 page  
MX29F4000
TABLE1. SOFTWARE COMMAND DEFINITIONS
Command
Reset
Read
Read Silicon ID
Sector Protect Verify
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Porgram
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Unlock for sector
protect/unprotect
Bus
Cycle
1
1
4
4
4
6
6
1
1
6
First Bus
Second Bus Third Bus Fourth Bus Fifth Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data
XXXH F0H
RA RD
555H AAH 2AAH 55H 555H 90H ADI DDI
555H AAH 2AAH 55H 555H 90H (SA)X 00H
02 01H
555H AAH 2AAH 55H 555H A0H PA PD
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
XXXH B0H
XXXH 30H
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
Sixth Bus
Cycle
Addr Data
555H 10H
SA 30H
555H 20H
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Do
not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 99H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A18 in either state.
4.For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected.If read out data
is 00H,it means the sector is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read
mode. Table 1 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device(when
applicable).
P/N:PM0629
REV. 1.0, DEC. 20, 1999
5
5 Page 
MX29F4000
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
www.DataSheet4U.com
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use the
other active sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incorrectly
used.
DATA PROTECTION
The MX29F4000 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific command sequences. The device also
incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and power-
down transition or system noise.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.
P/N:PM0629
REV. 1.0, DEC. 20, 1999
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 29F4000.PDF ] | |
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