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PDF MBM29LV320TE Data sheet ( Hoja de datos )
| Número de pieza | MBM29LV320TE | |
| Descripción | 32 M (4 M X 8/2 M X 16) BIT | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20894-1E
FLASH MEMORY
CMOS
32 M (4 M × 8/2 M × 16) BIT
MBM29LV320TE 80/90/10
MBM29LV320BE80/90/10
s DESCRIPTION
The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words
of 16 bits each. The device is offered in a 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed
to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required
for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microproces-
sors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE)
and output enable (OE) controls.
s PRODUCT LINE UP
(Continued)
Part No.
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MBM29LV320TE/BE
80 90
VCC
=
3.3
V +0.3
−0.3
V
V
80 90
80 90
30 35
100
VCC
=
3.0
V +0.6 V
−0.3 V
100
100
35
s PACKAGES
48-pin plastic TSOP (I)
Marking Side
48-pin plastic TSOP (I)
63-ball plastic FBGA
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-63P-M01)
1 page  
(Continued)
MBM29LV320TE/BE80/90/10
FBGA
(TOP VIEW)
Marking Side
A8 B8
N.C. N.C.
L8 M8
N.C. N.C.
A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7
N.C. N.C. A13 A12 A14 A15 A16 BYTE DQ15/ VSS N.C. N.C.
A-1
C6 D6 E6 F6 G6 H6 J6 K6
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
C5 D5 E5 F5 G5 H5 J5 K5
WE RESET N.C. A19 DQ5 DQ12 VCC DQ4
C4 D4 E4 F4 G4 H4 J4 K4
RY/BY WP/ A18 A20 DQ2 DQ10 DQ11 DQ3
ACC
C3 D3 E3 F3 G3 H3 J3 K3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A2
N.C.
C2 D2 E2 F2 G2 H2 J2 K2 L2 M2
A3 A4 A2 A1 A0 CE OE VSS N.C. N.C.
A1 B1
N.C. N.C.
L1 M1
N.C. N.C.
(BGA-63P-M01)
5
5 Page 
MBM29LV320TE/BE80/90/10
(Continued)
*1 : This command is valid during Fast Mode.
*2 : This command is valid while RESET = VID.
*3 : The valid addresses are A6 to A0.
*4 : This command is valid during Hi-ROM mode.
*5 : The data "00h" is also acceptable.
Notes: • Address bits A20 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA) .
• Bus operations are defined in “MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE
= VIL)” .
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12
will uniquely select any sector.
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
• SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0) .
SD = Sector group protection verify data. Output 01h at protected sector group addresses and
output 00h at unprotected sector group addresses.
• HRA = Address of the Hi-ROM area
29LV320TE (Top Boot Type) Word Mode : 1FFFE0h to 1FFFFFh
Byte Mode : 3FFFC0h to 3FFFFFh
29LV320BE (Bottom Boot Type) Word Mode : 000000h to 000040h
Byte Mode : 000000h to 000080h
• The system should generate the following address patterns :
Word Mode : 555h or 2AAh to addresses A10 to A0
Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command combinations not described in “MBM29LV320TE/BE Command Definition Table” are
illegal.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MBM29LV320TE.PDF ] | |
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