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PDF MBM29F002TC Data sheet ( Hoja de datos )
| Número de pieza | MBM29F002TC | |
| Descripción | 2M (256K x 8) BIT FLASH MEMORY | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
2M (256K × 8) BIT
DS05-20868-3E
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
s FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
• 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
32-pin PLCC (Package Suffix: PD)
• Minimum 100,000 write/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
Any combination of sectors can be erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
• Sector protection
Hardware method that disables any combination of sector from write or erase operation
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
1 page  
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
s PRODUCT LINE UP
Part No.
MBM29F002TC/BC
VCC = 5.0 V ± 5%
-55
—
—
Ordering Part No.
VCC = 5.0 V ± 10%
—
-70
-90
Max. Address Access Time (ns) 55 70 90
Max. CE Access Time (ns)
55 70 90
Max. OE Access Time (ns)
30 30 35
s BLOCK DIAGRAM
VCC
VSS
WE
RESET
CE
OE
DQ0 to DQ7
Erase Voltage
Generator
Input/Output
Buffers
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
A0 to A17
STB Y-Decoder
Low VCC Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29F002TC-55/-70/-90/MBM29F002BC-55/-70/-90
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F002TC/BC features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 6). The sector protection feature is enabled using programming
equipment at the user's site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL. The sector addresses (A13, A14, A15, A16, and A17) should be set to the sector to be
protected. Tables 4 and 5 define the sector address for each of the seven (7) individual sectors. Programming
of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of
the same. Sector addresses must be held constant during the WE pulse. See figures 14 and 21 for sector
protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A13, A14, A15, A16, and A17) while (A10, A6,
A1, A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
device will produce 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A6,
and A10 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device
codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A13, A14, A15, A16, and A17)
are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See Table 3 for Autoselect
codes.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MBM29F002TC.PDF ] | |
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