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PDF KM48S8030C Data sheet ( Hoja de datos )
| Número de pieza | KM48S8030C | |
| Descripción | 2M x 8Bit x 4 Banks Synchronous DRAM | |
| Fabricantes | Samsung semiconductor | |
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KM48S8030C
Revision History
Revision 0.0 (Oct., 1998)
• PC133 first published.
Preliminary
PC133 CMOS SDRAM
REV. 0 Oct. '98
1 page  
KM48S8030C
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS
Latency
Operating current
(One bank active)
ICC1
Burst length = 1
tRC ≥ tRC(min)
IOL = 0 mA
Precharge standby current in
power-down mode
Precharge standby current in
non power-down mode
ICC2P CKE ≤ VIL(max), tCC = 15ns
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P CKE ≤ VIL(max), tCC = 15ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
Operating current
(Burst mode)
IOL = 0 mA
ICC4
Page burst
2Banks activated
tCCD = 2CLKs
3
-
Refresh current
ICC5 tRC ≥ tRC(min)
Self refresh current
ICC6 CKE ≤ 0.2V
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM48S8030CT-G**
4. KM48S8030CT-F**
Preliminary
PC133 CMOS SDRAM
Version
-A
75
1
1
12
6
2
2
20
10
110
-
125
1
450
Unit Note
mA 1
mA
mA
mA
mA
mA
mA 1
mA 2
mA 3
uA 4
REV. 0 Oct. '98
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet KM48S8030C.PDF ] | |
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