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PDF TC9444F Data sheet ( Hoja de datos )
| Número de pieza | TC9444F | |
| Descripción | Single-Chip karaoke IC II | |
| Fabricantes | Toshiba Semiconductor | |
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9444F
Single-Chip karaoke IC II
TC9444F
The TC9444F is a karaoke chip for such applications as
equipment for CD/LD players, mini component stereo sets,
radio-cassette players, and VTRs.
With its internal AD/DA converter system, the TC9444F can
offer such karaoke functions as echo, vocal canceling, and key
control on a single chip in addition to such digital signal
processing (DSP) features as sound field control and bass/treble
control.
Because the program and coefficients are stored on internal
ROM, the IC can be controlled by simple settings.
Features
Weight: 1.08 g (typ.)
· Incorporates an AD converter (three channels) with 2 times oversampling.
THD: −65dB S/N ratio: 80dB (typ.)
built-in pre-filter op-amp
· Incorporates a 1-bit Σ∆-type DA converter (two channels).
THD: −86dB S/N ratio: 93dB (typ.)
built-in tertiary analog post filter
· Supports one port for digital input and one for digital output.
· Incorporates 64 Kbits of delay RAM
· Microcontroller interface: I2C bus mode as well as Toshiba’s original three-lead mode
· Built-in boot ROM initializes coefficients at reset or via a boot command.
[Compatible Software]
· Microphone echo: Variable delay time/level
· Vocal cancellation: Attenuates only vocals from standard source
· Vocal change: Vocals fade in/out depending on whether there is input from microphone
· Vocal key control: For chorus and duet functions
· Supports multi-sound sources: Various modes
· Pseudo stereo: Monaural sources enhanced by sense of spaciousness
· Key control: 14-step (max ±1 octave) stereo key control
· Compressor or bass boost: Compression ratio selectable in range 6 to 36dB.
Compression effect (amount of boost) can be varied smoothly.
· Sound field control: Uses delay RAM to simulate such acoustic environments as churches, halls, sports
stadiums, and discos.
· Equalizer: Characteristics switchable by coefficient or I/F bit settings
· 3D sound field: Offers 3-D sound.
1 2002-01-11
1 page  
Block Operations
TC9444F
1. Operating Clocks
The master clock can be selected between 512 or 384 fs using the CKS pin. The master clock uses
oscillator or external clock input, through the XI pin.
Regardless of a master clock, the number of digital signal processing steps are predetermined. However,
the DA converter’s operating clock varies according to the master clock mode.
The MCKS pin sets the MCKO output, selecting 1/1 or 1/2 divider of the XI pin.
Table 1.1 Operating Clock Selection and DA Converter Oversampling Rate
CKS Pin
L
H
MCKS Pin
L
H
L
H
XI Input
384 fs
512 fs
MCKO Output
192 fs
384 fs
256 fs
512 fs
DAC Oversampling Rate
192 fs
256 fs
2. Digital Audio Data Input/Output
2.1 Sync Mode
The data input/output bit clock and internal sync (master) mode or external sync (slave) mode are
set using microcontroller interface bits SYNM1 and SYNM2. Initialization by reset sets master mode.
Table 2.1 Sync Mode and Input/Output Bit Clock Settings
SYNM2
SYNM1 SYNC Mode
0 0 Master
0 1 Slave
1 0 Slave
1 1 Slave
Note 1: See Table 2.2.
Note 2: XI input divider clock
BCKI
(Note 1)
32 fs
48 fs
64 fs
BCKO
64 fs
(Note 2)
BCKI
BCKI
BCKI
5 2002-01-11
5 Page 
TC9444F
3.2 BOOT Command
One-byte command to initialize coefficient RAM.
Initializes coefficient RAM values to the internal BOOT ROM values, retaining the other command
interface settings.
After the BOOT command is received, initialization completes in a 1-fs cycle. Boot release is not
required.
When reset is made by setting the RESET pin to “L”, boot is still executed.
3.3 MUTE Command
One-byte command to clear data RAM and delay RAM, and to execute a soft mute using the digital
attenuator.
Table 3.2 MUTE Command
CH
3
10
CL
21
0 RAMCLR
0
MUTE
Note 5: At a reset, the initial value is CL = 0H.
MUTE: MUTE = “H” sets soft mute.
RAMCLR: RAMCLR = “H” clears data RAM and delay RAM.
At a soft mute, the time constant is determined by the operation sampling frequency and the time
constant selection bit set by the ATTA command. After the soft mute is released, the digital
attenuator is restored to the set level.
In data RAM, sequentially writing all-zero data (fixing the input data to 000000H) while RAMCLR
= “H” clears data RAM. Therefore, the number of fs cycles required to completely clear data RAM
depends on the program. Normally, several cycles are required.
For a program which is written to in one place only, a 128-word update takes no more than 3 ms.
In delay RAM, after RAMCLR = H, 0000H is sequentially written to delay RAM at subsequent
write operations (INIT operation).
When using delay RAM to significantly change the effect of the SFC processing, to clear the data in
RAM, take the following steps. First set the MUTE bit. Then, after waiting only the length of the
digital attenuator time constant, set RAMCLR to “H” to clear the data in RAM. Then set the
RAMCLR and MUTE bits to “L”. This will enable you to change the signal processing content without
any switching noise.
3.4 KEYCON Command
One-byte command to control the amount of key shift. The CL value indicates the amount of key
shift.
The difference between the 20H command and the 28H command is the point at which key control
processing completely stops. Using the 20H command to turn key control off disables the use of
internal delay RAM in the key control processing, thus allowing delay RAM to be allocated to other
processing.
The amount of key shift set by the KEYCON command applies to both L and R stereo key control
and to monaural key control. The key shift is set in semitone steps.
As delay RAM is used in key control processing, when switching the key shift setting between 0 and
a value other than 0, the signal is intermittent. The soft mute automatically comes on to avoid
switching noise at this time. After the command is issued, the following steps are performed
automatically.
Mute ® Internal settings switched ® Mute released
This series of processing operations takes around 46 ms to execute.
11 2002-01-11
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