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PDF K4E640812E Data sheet ( Hoja de datos )
| Número de pieza | K4E640812E | |
| Descripción | (K4E640812E / K4E660812E) 8M x 8bit CMOS Dynamic RAM with Extended Data Out | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K4E660812E,K4E640812E
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using
Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4E660812E-JC/L(3.3V, 8K Ref.)
- K4E640812E-JC/L(3.3V, 4K Ref.)
- K4E660812E-TC/L(3.3V, 8K Ref.)
- K4E640812E-TC/L(3.3V, 4K Ref.)
• Active Power Dissipation
Speed
-45
-50
-60
8K
324
288
252
Unit : mW
4K
432
396
360
• Refresh Cycles
Part Refresh
NO. cycle
K4E660812E*
K4E640812E
8K
4K
Refresh time
Normal L-ver
64ms 128ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
¡Ü Performance Range:
Speed
-45
tRAC
45ns
tCAC
12ns
-50 50ns 13ns
-60 60ns 15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V ±0.3V power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
8,388,608 x 8
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ7
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
1 page  
K4E660812E,K4E640812E
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Input capacitance [RAS, CAS , W, OE]
Output capacitance [DQ0 - DQ7]
Symbol
CI N 1
CI N 2
C DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)
Test condition : VCC =3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-45
Min Max
Random read or write cycle time
tR C 74
Read-modify-write cycle time
tR W C
101
Access time from RAS
Access time from CAS
tR A C
tC A C
45
12
Access time from column address
tA A
23
CAS to output in Low-Z
tCLZ
3
Output buffer turn-off delay from CAS
tC E Z
3 13
OE to output in Low-Z
tOLZ
3
Transition time (rise and fall)
RAS precharge time
tT 1 50
tR P 25
RAS pulse width
tR A S
45 10K
RAS hold time
tR S H
8
CAS hold time
tC S H
35
CAS pulse width
tC A S
7 5K
RAS to CAS delay time
RAS to column address delay time
tRCD
tR A D
11 33
9 22
CAS to RAS precharge time
tC R P
5
Row address set-up time
tASR
0
Row address hold time
tR A H
7
Column address set-up time
Column address hold time
tASC
tC A H
0
7
Column address to RAS lead time
tR A L
23
Read command set-up time
tR C S
0
Read command hold time referenced to CAS tRCH
0
Read command hold time referenced to RAS tRRH
0
Write command hold time
Write command pulse width
tW C H
tW P
7
6
Write command to RAS lead time
tR W L
8
Write command to CAS lead time
tC W L
7
Data set-up time
tD S 0
-50
Min Max
84
113
50
13
25
3
3 13
3
1 50
30
50 10K
8
38
8 10K
11 37
9 25
5
0
7
0
7
25
0
0
0
7
7
8
7
0
-60
Min Max
104
138
60
15
30
3
3 13
3
1 50
40
60 10K
10
40
10 10K
14 45
12 30
5
0
10
0
10
30
0
0
0
10
10
10
10
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
3,4,10
3,4,5
3,10
3
6,13
3
2
14
4
10
8
8
9
5 Page 
K4E660812E,K4E640812E
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ3(7)
VIH -
VIL -
tRAS
tRC
tCRP
tRCD
tRAD
tASR
tRAH
ROW
ADDRESS
tASC
tCSH
tRSH
tCAS
tR A L
tC A H
COLUMN
ADDRESS
tCWL
tRWL
tWP
tOED
tOEH
tDS
tDH
DATA-IN
CMOS DRAM
tRP
tCRP
Don′t care
Undefined
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet K4E640812E.PDF ] | |
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