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PDF M470L6423EN Data sheet ( Hoja de datos )
| Número de pieza | M470L6423EN | |
| Descripción | 512MB Unbuffered SODIMM(based on sTSOP) | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
DDR SDRAM Unbuffered SODIMM
200pin Unbuffered SODIMM based on 256Mb E-die (x8)
with 64-bit Non ECC
Revision 1.3
March. 2004
Rev. 1.3 March. 2004
1 page  
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
DQS0
DM0
DQS1
DM1
DQS2
DM2
DQS3
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS0
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D0
CS DQS
D1
CS DQS
D2
CS DQS
D3
CS1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS4
DM4
CS DQS
D8
DQS5
DM5
CS DQS
D9
DQS6
DM6
CS DQS
D10
DQS7
DM7
CS DQS
D11
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D12
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D13
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D14
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
BA0 - BA1
A0 - A12
RAS
CAS
CKE1
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D15
A0-A12 : DDR SDRAMs D0 - D15
RAS : DDR SDRAMs D0 - D15
CAS : DDR SDRAMs D0 - D15
CKE : DDR SDRAMs D8 - D15
CKE : DDR SDRAMs D0 - D7
WE : DDR SDRAMs D0 - D15
R=120Ω
± 5%
CK0 / 1
CK0 / 1 Card
Edge
D0,D8 / D4,D12
D1,D9 / D5,D13
D2,D10/ D6,D14
CK2
CK2
D3,D11/ D7,D15
*Clock Net Wiring
10pF
VDDSPD
VDD/VDDQ
VREF
VSS
SPD
D0 - D15
D0 - D15
D0 - D15
D0 - D15
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown
3. DQ, DQS, DM/DQS resistors: 22 Ohm.
Rev. 1.3 March. 2004
5 Page 
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
8. I/O Setup/Hold Plateau Derating
I/O Input Level
∆tDS
∆tDH
(mV)
(ps) (ps)
± 280
+50 +50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
∆tDS
∆tDH
(ns/V)
(ps) (ps)
0 00
±0.25
+50 +50
±0.5
+100
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
(Single ended)
∆tIH/tIS
(ps)
∆tDSS/tDSH ∆tAC/tDQSCK
(ps) (ps)
∆tLZ(min)
(ps)
∆tHZ(max)
(ps)
1.0V/ns
00000
0.75V/ns
+50 +50 +50 -50 +50
0.5V/ns
+100
+100
+100
-100
+100
Rev. 1.3 March. 2004
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet M470L6423EN.PDF ] | |
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