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PDF M50FLW080 Data sheet ( Hoja de datos )
| Número de pieza | M50FLW080 | |
| Descripción | Low Pin Count Flash Memory | |
| Fabricantes | ST Microelectronics | |
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M50FLW080A
M50FLW080B
8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)
3V Supply Firmware Hub / Low Pin Count Flash Memory
FEATURES SUMMARY
■ FLASH MEMORY
– Compatible with either the LPC interface
or the FWH interface (Intel Spec rev1.1)
used in PC BIOS applications
– 5 Signal Communication Interface
supporting Read and Write Operations
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
■ 16 BLOCKS OF 64 KBYTES
– 13 blocks of 64 KBytes each
– 3 blocks, subdivided into 16 uniform
sectors of 4 KBytes each
Two blocks at the top and one at the
bottom (M50FLW080A)
One block at the top and two at the bottom
(M50FLW080B)
■ ENHANCED SECURITY
– Hardware Write Protect Pins for Block
Protection
– Register-based Read and Write
Protection
– Individual Lock Register for Each 4 KByte
Sector
■ SUPPLY VOLTAGE
– VCC = 3.0 to 3.6V for Program, Erase and
Read Operations
– VPP = 12V for Fast Program and Erase
■ TWO INTERFACES
– Auto Detection of Firmware Hub (FWH) or
Low Pin Count (LPC) Memory Cycles for
Embedded Operation with PC Chipsets
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
■ PROGRAMMING TIME: 10µs typical
■ PROGRAM/ERASE CONTROLLER
– Embedded Program and Erase algorithms
– Status Register Bits
Figure 1. Packages
PLCC32 (K)
TSOP32 (NB)
8 x 14mm
TSOP40 (N)
10 x 20mm
■ PROGRAM/ERASE SUSPEND
– Read other Blocks/Sectors during
Program Suspend
– Program other Blocks/Sectors during
Erase Suspend
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (M50FLW080A): 80h
– Device Code (M50FLW080B): 81h
June 2005
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1 page  
M50FLW080A, M50FLW080B
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 34. M50FLW080A Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 41
Table 35. M50FLW080B Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . . 46
Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 47
Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 48
Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 49
Figure 27.Sector/Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 51
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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5 Page 
M50FLW080A, M50FLW080B
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
driven Low, VIL, Program and Erase operations in
the Main Blocks have no effect, regardless of the
state of the Lock Register. When Write Protect,
WP, is driven High, VIH, the protection of the Block
or Sector is determined by the Lock Registers. The
state of Write Protect, WP, does not affect the pro-
tection of the Top Block (Block 15). For details,
see APPENDIX A..
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated, and must not be
changed until the operation has completed other-
wise unpredictable results may occur. Similarly,
unpredictable behavior is possible if WP is
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Reserved for Future Use (RFU). Reserved for
Future Use (RFU). These pins do not presently
have assigned functions. They must be left discon-
nected, except for ID0 and ID1 (when in LPC
mode) which can be left connected. The electrical
characteristics for these signals are as described
in the “Identification Inputs (ID0-ID3).” section.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
Please see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is to be written to
or read from the memory. They output the data
stored at the selected address during a Bus Read
operation. During Bus Write operations they carry
the commands that are sent to the Command In-
terface of the internal state machine. The Data In-
puts/Outputs, DQ0-DQ7, are latched during a Bus
Write operation.
Output Enable (G). The Output Enable signal, G,
controls the output buffers during a Bus Read op-
eration.
Write Enable (W). The Write Enable signal, W,
controls the Bus Write operation of the Command
Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs are to be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on its rising edge.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (read, pro-
gram, erase, etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This is to prevent Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time, the operation aborts, and the memory
contents that were being altered will be invalid. Af-
ter VCC becomes valid, the Command Interface is
reset to Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program command
description in A/A Mux interface and the Double/
Quadruple Byte Program command description in
FWH mode) and Fast Erase options of the memo-
ry.
When VPP = VCC, program and erase operations
take place as normal. When VPP = VPPH, Fast Pro-
gram and Erase operations are used. Any other
voltage input to VPP will result in undefined behav-
ior, and should not be used.
VPP should not be set to VPPH for more than
80 hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt-
age measurements.
11/53
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| PDF Descargar | [ Datasheet M50FLW080.PDF ] | |
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