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PDF XPC7445 Data sheet ( Hoja de datos )
| Número de pieza | XPC7445 | |
| Descripción | RISC Microprocessor Hardware Specifications | |
| Fabricantes | Freescale Semiconductor | |
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Advance Information
MPC7455RXNXPNS
Rev. 1.1, 1/2004
MPC7455 Part Number
Specification for the
XPC74x5RXnnnNx Series
Freescale Semiconductor, Inc.
Motorola Part
Numbers Affected:
XPC7455RX600NC
XPC7455RX733NC
XPC7455RX800NC
XPC7445RX600NC
XPC7445RX733NC
XPC7445RX800NC
This document describes part-number-specific changes to recommended operating conditions
and revised electrical specifications, as applicable, from those described in the general
MPC7455 RISC Microprocessor Hardware Specifications (Order No. MPC7455EC). The
MPC7455 is a PowerPC™ microprocessor.
Specifications provided in this document supersede those in the MPC7455 RISC
Microprocessor Hardware Specifications, Rev. 0 or later, for the part numbers listed in
Table A only. Specifications not addressed herein are unchanged. Because this document is
frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola
sales office for the latest version.
Note that headings and table numbers in this document are not consecutively numbered. They
are intended to correspond to the heading or table affected in the general hardware
specification.
Part numbers addressed in this document are listed in Table A.
Table A. Part Numbers Addressed by this Data Sheet
Motorola
Part Number
Operating Conditions
CPU
Frequency
(MHz)
VDD
Tj
(°C)
Significant Differences from
Hardware Specification
XPC7455RX600NC
XPC7455RX733NC
600 1.3 V ± 50 mV 0 to 105 Modified core and VCO frequency,
and power consumption specifications
733
XPC7455RX800NC
800
XPC7445RX600NC
600
XPC7445RX733NC
733
XPC7445RX800NC
800
Note: The X prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by
Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested,
and Q.A. inspected on a qualified technology to simulate normal production. These parts have only
preliminary reliability and characterization data. Before pilot production prototypes may be shipped,
written authorization from the customer must be on file in the applicable sales office acknowledging the
qualification status and the fact that product changes may still occur while shipping pilot production
prototypes.
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
General Parameters
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See Table 4.
Parameter
All Speed Grades
Symbol L2CR[12] = 0 and L3CR[12] = 08 L2CR[12] = 1 and L3CR[12] = 18 Unit Notes
Min Max Min Max
L3_CLK to high
tL3CHOZ
—
tL3_CLK/4 + 2.0
—
tL3_CLK/4 + 2.0 ns
impedance:
All other outputs
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage
of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor
Hardware Specifications). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the MPC7455
RISC Microprocessor Hardware Specifications. For consistency with other input setup time specifications, this will
be treated as negative input setup time.
4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7455 can latch
an input signal that is valid for only a short time before and a short time after the midpoint between the rising and
falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling)
edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output
timings assume a purely resistive 50-Ω load (see Figure 8 in the MPC7455 RISC Microprocessor Hardware
Specifications).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the MPC7455 RISC
Microprocessor Hardware Specifications. For consistency with other output valid time specifications, this will be
treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock
period after the edge it will be sampled.
8. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or
both cleared; other configurations will increase tL3CSKW1, which may cause unreliable L3 operation.
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series
For More Information On This Product,
Go to: www.freescale.com
5
5 Page 
Freescale Semiconductor, Inc.
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series
For More Information On This Product,
Go to: www.freescale.com
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet XPC7445.PDF ] | |
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