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Integrated Device Technology - HIGH-SPEED 3.3V 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

Numéro de référence IDT70V9289L
Description HIGH-SPEED 3.3V 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT70V9289L fiche technique
HIGH-SPEED 3.3V 64K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70V9289L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
x Low-power operation
– IDT70V9289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
4ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode
x Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x LVTTL- compatible, single 3.3V (±0.3V) power supply
x Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x Available in a 128-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O8L-I/O15L
I/O0L-I/O7L
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
1b 0b
b
a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
0a 1a
a
b0b 1b
0/1
Counter/
Address
Reg.
FT/PIPER
I/O8R-I/O15R
I/O0R-I/O7R
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4855 drw 01
©2000 Integrated Device Technology, Inc.
1
JUNE 2000
DSC-4855/1

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