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PDF AD5381 Data sheet ( Hoja de datos )
| Número de pieza | AD5381 | |
| Descripción | Voltage Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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40-Channel, 3 V/5 V, Single-Supply,
12-Bit, Voltage Output DAC
AD5381
FEATURES
INTEGRATED FUNCTIONS
Guaranteed monotonic
Channel monitor
INL error: ±1 LSB max
Simultaneous output update via LDAC
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Clear function to user programmable code
Temperature range: –40°C to +85°C
Amplifier boost mode to optimize slew rate
Rail-to-rail output amplifier
User programmable offset and gain adjust
Power-down
Toggle mode enables square wave generation
Package type: 100-lead LQFP (14 mm × 14 mm)
Thermal monitors
User Interfaces:
Parallel
Serial (SPI®/QSPI™/MICROWIRE™/DSP compatible,
featuring data readback)
I2C® compatible
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMs)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVDD (×3)
DGND (×3)
AVDD (×5)
AGND (×5) DAC GND (×5)
REFGND REFOUT/REFIN SIGNAL GND (×5)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD 0)
WR/(DCEN/AD 1)
SDO
AD5381
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I2C)
DB8
DB0
A5
A0
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
REG 0
REG 1
RESET
BUSY
CLR
POWER-ON
RESET
VOUT 0………VOUT 38
39-TO-1
MUX
12 INPUT 12
REG 0
12 m REG 0
12 c REG 0
12 INPUT 12
REG 1
12 m REG 1
12 c REG 1
12 INPUT 12
REG 6
12 m REG 6
12 c REG 6
12 INPUT 12
REG 7
12 m REG 7
12 c REG 7
×5
1.25V/2.5V
REFERENCE
12
DAC 12
REG 0
DAC 0
12
DAC 12
REG 1
DAC 1
12
DAC 12
REG 6
DAC 6
12
DAC 12
REG 7
DAC 7
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT38
VOUT 39/MON_OUT
Figure 1.
LDAC
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD5381
Parameter
LOGIC OUTPUTS (BUSY, SDO)3
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)3
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity3
∆Midscale/∆ΑVDD
AIDD
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
AD5381-51
0.4
DVDD – 1
0.4
DVDD – 0.5
±1
5
0.4
0.6
±1
8
4.5/5.5
2.7/5.5
–85
0.375
0.475
1
2
20
80
Unit
V max
V min
V max
V min
µA max
pF typ
V max
V max
µA max
pF typ
V min/max
V min/max
dB typ
mA/channel max
mA/channel max
mA max
µA max
µA max
mW max
Test Conditions/Comments
DVDD = 5 V ± 10%, sinking 200 µA
DVDD = 5 V ± 10%, sourcing 200 µA
DVDD = 2.7 V to 3.6 V, sinking 200 µA
DVDD = 2.7 V to 3.6 V, sourcing 200 µA
SDO only
SDO only
ISINK = 3 mA
ISINK = 6 mA
Outputs unloaded, Boost off. 0.25 mA/channel typ.
Outputs unloaded, Boost on. 0.325 mA /channel typ.
VIH = DVDD, VIL = DGND
Outputs unloaded, Boost off, AVDD = DVDD = 5 V
1 AD5381-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.
2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3 Guaranteed by characterization, not production tested.
4 Default on the AD5381-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5381 control register; operating the AD5381-5 with a 1.25 V reference will lead to
degraded accuracy specifications.
Rev. A | Page 5 of 36
5 Page 
PARALLEL INTERFACE TIMING
Table 8. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted
Parameter1,2,3
Limit at TMIN, TMAX
Unit Description
t0 4.5
ns min
REG0, REG1, address to WR rising edge setup time
t1 4.5
ns min
REG0, REG1, address to WR rising edge hold time
t2 20
ns min
CS pulse width low
t3 20
ns min
WR pulse width low
t4 0
ns min
CS to WR falling edge setup time
t5 0
ns min
WR to CS rising edge hold time
t6 4.5
ns min
Data to WR rising edge setup time
t7 4.5
ns min
Data to WR rising edge hold time
t8 20
ns min
WR pulse width high
t94 700
ns min
Minimum WR cycle time (single-channel write)
t104 30
ns max
WR rising edge to BUSY falling edge
t114, 5
670
ns max
BUSY pulse width low (single-channel update)
t12 30
ns min
WR rising edge to LDAC falling edge
t13 20
ns min
LDAC pulse width low
t14 100
ns max
BUSY rising edge to DAC output response time
t15 20
ns min
LDAC rising edge to WR rising edge
t16 0
ns min
BUSY rising edge to LDAC falling edge
t17 100
ns min
LDAC falling edge to DAC output response time
t18 8
µs typ
DAC output settling time, boost mode off
t19 20
ns min
CLR pulse width low
t20 12
µsmax
CLR pulse activation time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 7.
4 See Figure 29.
5 Measured with the load circuit of Figure 2.
AD5381
Rev. A | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5381.PDF ] | |
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