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UPA2702GR fiches techniques PDF

NEC - SWITCHING N- AND P-CHANNEL POWER MOS FET

Numéro de référence UPA2702GR
Description SWITCHING N- AND P-CHANNEL POWER MOS FET
Fabricant NEC 
Logo NEC 





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UPA2702GR fiche technique
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA2702GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The µPA2702GR is N-Channel MOS Field Effect Transistor
designed for DC/DC converters and power management
applications of notebook computers.
FEATURES
Low on-state resistance
RDS(on)1 = 9.5 mMAX. (VGS = 10 V, ID = 7.0 A)
RDS(on)2 = 15.1 mMAX. (VGS = 4.5 V, ID = 7.0 A)
Low Ciss: Ciss = 900 pF TYP. (VDS = 10 V, VGS = 0 V)
Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
µPA2702GR
PACKAGE
Power SOP8
PACKAGE DRAWING (Unit: mm)
85
1, 2, 3 ; Source
4 ; Gate
5, 6, 7, 8 ; Drain
14
5.37 MAX.
6.0 ±0.3
4.4
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.8
0.10
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation (TA = 25°C) Note2
ID(DC)
ID(pulse)
PT
±13
±52
2.0
A
A
W
Channel Temperature
Tch 150 °C
Storage Temperature
Single Avalanche Current Note3
Single Avalanche Energy Note3
Tstg –55 to +150 °C
IAS 13
A
EAS 16.9 mJ
EQUIVALENT CIRCUIT
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW 10 µs, Duty Cycle 1%
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
5 3. Starting Tch = 25°C, VDD = 15 V, RG = 25 , L = 100 µH, VGS = 20 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is extemally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G15724EJ2V0DS00 (2nd edition)
Date Published May 2002 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
2002

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