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PDF DS1501 Data sheet ( Hoja de datos )
| Número de pieza | DS1501 | |
| Descripción | (DS1501 / DS1511) Y2K-Compliant Watchdog Real-Time Clocks | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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www.maxim-ic.com
GENERAL DESCRIPTION
The DS1501/DS1511 are full-function, year 2000-
compliant real-time clock/calendars (RTCs) with an
RTC alarm, watchdog timer, power-on reset, battery
monitors, 256 bytes NV SRAM, and a 32.768kHz
output. User access to all registers within the
DS1501/DS1511 is accomplished with a byte-wide
interface, as shown in Figure 8. The RTC registers
contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour binary-coded
decimal (BCD) format. Corrections for day of month
and leap year are made automatically.
APPLICATIONS
Remote Systems
Battery-Backed Systems
Telecom Switches
Office Equipment
Consumer Electronics
ORDERING INFORMATION
PART
DS1501YN
DS1501YEN
DS1501YSN
DS1501WN
DS1501WEN
DS1501WSN
DS1511Y
DS1511W
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 DIP (600 mil)
28 TSOP
28 SO (330 mil)
28 DIP (600 mil)
28 TSOP
28 SO (330 mil)
28 Module (720 mil)
28 Module (720 mil)
Selector Guide appears at end of data sheet.
Typical Operating Circuits appears at end of data sheet.
DS1501/DS1511
Y2K-Compliant Watchdog
Real-Time Clocks
FEATURES
§ BCD-Coded Century, Year, Month, Date, Day,
Hours, Minutes, and Seconds with Automatic
Leap-Year Compensation Valid Up to the Year
2100
§ Programmable Watchdog Timer and RTC Alarm
§ Century Register; Y2K-Compliant RTC
§ +3.3 or +5V Operation
§ Precision Power-On Reset
§ Power-Control Circuitry Support System Power-
On from Date/Day/Time Alarm or Key
Closure/Modem-Detect Signal
§ 256 Bytes Battery-Backed NV SRAM
§ Auxiliary Battery Input
§ Accuracy of DS1511 Better than ±1
Minute/Month at +25°C
§ Day-of-Week/Date Alarm Register
§ Crystal Select Bit Allow RTC to Operate with 6pF
or 12.6pF Crystal
§ Battery Voltage-Level Indicator Flags
§ Available as Chip (DS1501) or Stand-Alone
Module with Embedded Battery and Crystal
(DS1511)
§ UL Recognized
PIN CONFIGURATION
TOP VIEW
PWR
X1
X2
RST
IRQ
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 28
2 27
3 26
4 25
5
Dallas
Semiconductor
24
6 DS1501 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
VBAUX
VBAT
KS
SQW
OE
GND
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DIP, SO
Pin Configurations are continued at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 031704
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DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
Figure 2. Write Cycle Timing, Write-Enable Controlled
A0–A4
CE
WE
DQ0–DQ7
tWC
VALID
tAS
VALID
tAH
tAS tWEW tWR
DATA OUTPUT
tWEZ
tDS tDH
DATA INPUT
DATA INPUT
Figure 3. Write Cycle Timing, Chip-Enable Controlled
A0-A4
CE
WE
DQ0-DQ7
tWC
VALID
tAS tCEW
VALID
tAH
tAS tWR
tDS
DATA INPUT
tDH
DATA INPUT
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DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
DETAILED DESCRIPTION
The RTC registers are double buffered into an internal and external set. The user has direct access to the external
set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access
static data. When the crystal oscillator is turned on, the internal set of registers are continuously updated; this
occurs regardless of external register settings to guarantee that accurate RTC information is always maintained.
The DS1501/DS1511 contain their own power-fail circuitry that automatically deselects the device when the VCC
supply falls below a power-fail trip point. This feature provides a high degree of data security during unpredictable
system operation caused by low VCC levels.
The DS1501/DS1511 have interrupt (IRQ), power control (PWR), and reset (RST) outputs that can be used to
control CPU activity. The IRQ interrupt or RST outputs can be invoked as the result of a time-of-day alarm, CPU
watchdog alarm, or a kickstart signal. The DS1501/DS1511 power-control circuitry allow the system to be powered
on by an external stimulus, such as a keyboard or by a time and date (wakeup) alarm. The PWR output pin can be
triggered by one or either of these events, and can be used to turn on an external power supply. The PWR pin is
under software control, so that when a task is complete, the system power can then be shut down. The
DS1501/DS1511 power-on reset can be used to detect a system power-down or failure and hold the CPU in a safe
reset state until normal power returns and stabilizes; the RST output is used for this function.
The DS1501/DS1511 are clock/calendar chips with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
Table 1. RTC Operating Modes
VCC
In tolerance
VSO < VCC < VPF
VCC < VSO < VPF
CE OE WE
VIH X X
VIL X VIL
VIL VIL VIH
VIL VIH VIH
X XX
X XX
DQ0–DQ7
High-Z
DIN
DOUT
High-Z
High-Z
High-Z
A0–A4
X
AIN
AIN
AIN
X
X
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1501/DS1511 are in read mode whenever CE (chip enable) and OE (output enable) are low and WE (write
enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data is
available at the DQ pins within tAA (address access) after the last address input is stable, provided that CE and OE
access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of chip-enable
access (tCSA) or at output-enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE
and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the
address inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time (tOH)
but then goes indeterminate until the next address access (Table 1).
DATA WRITE MODE
The DS1501/DS1511 are in write mode whenever CE and WE are in their active state. The start of a write is
referenced to the latter occurring transition of CE or WE. The addresses must be held valid throughout the cycle.
CE or WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data
in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE
signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid
bus contention. If OE is low prior to a high-to-low transition on WE, the data bus can become active with read data
defined by the address inputs. A low transition on WE then disables the outputs tWEZ after WE goes active (Table 1).
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet DS1501.PDF ] | |
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