PDF DS1557 Data sheet ( Hoja de datos )

Número de pieza	DS1557
Descripción	4MEG NV Y2KC Timekeeping RAM
Fabricantes	Dallas Semiconducotr
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PRELIMINARY DS1557 4MEG NV Y2KC Timekeeping RAM www.dalsemi.com FEATURES Integrated NV SRAM, real time clock, crystal, power-fail control circuit and lithium energy source Clock registers are accessed identically to the static RAM; these registers are resident in the 16 top RAM locations Century byte register; i.e., Y2K complaint Totally nonvolatile with over 10 years of operation in the absence of power Precision power-on reset Programmable watchdog timer and RTC alarm BCD coded year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 Battery voltage level indicator flag Power-fail write protection allows for ±10% VCC power supply tolerance Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ORDERING INFORMATION DS1557P-XXX (5-Volt) -70 70 ns access -100 100 ns access DS1557WP-XXX (3.3 Volt) -120 120 ns access -150 150 ns access DS9034PCX (PowerCap) Required: must be ordered seperately PIN ASSIGNMENT IRQ/FT 1 34 A15 A16 RST VCC WE OE CE DQ7 2 3 4 5 6 7 8 9 33 32 31 30 29 28 27 26 DQ6 10 25 DQ5 DQ4 11 12 24 23 DQ3 13 22 DQ2 DQ1 DQ0 14 21 15 16 X1 GND VBAT X2 20 19 GND 17 18 A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin POWERCAP MODULE BOARD (USES DS9034PCX POWERCAP) PIN DESCRIPTION A0-A14 - Address Input DQ0-DQ7 - Data Input/Outputs IRQ \FT - Interrupt, Frequency Test Output (Open Drain) RST - Power-On Reset Output (Open Drain) CE - Chip Enable OE - Output Enable WE VCC GND NC X1, X2 VBAT - Write Enable - Power Supply Input - Ground - No Connection - Crystal Connection - Battery Connection DESCRIPTION The DS1557 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC alarm, watchdog timer, power-on reset, battery monitor, and 512k x 8 non-volatile static RAM. User access to all registers within the DS1557 is accomplished with a bytewide interface as shown in Figure 1. The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. 1of 19 012700 1 page DS1557 REGISTER MAP Table 2 DATA ADDRESS B7 B6 B5 B4 B3 7FFFh 10 Year 7FFEh X X X 10 M 7FFDh X X 10 Date 7FFCh X FT X X X 7FFBh X X 10 HOUR 7FFAh X 10 MINUTES 7FF9h OSC 10 SECONDS 7FF8h W R 10 CENTURY 7FF7h WDS BMB4 BMB3 BMB2 BMB1 7FF6h AE Y ABE Y Y 7FF5h AM4 Y 10 DATE 7FF4h AM3 Y 10 HOURS 7FF3h AM2 10 MINUTES 7FF2h AM1 10 SECONDS 7FF1h Y Y Y Y Y 7FF0h WF AF 0 BLF 0 B2 B1 YEAR MONTH DATE DAY HOUR MINUTES SECONDS CENTURY BMB0 RB1 YY DATE HOURS MINUTES SECONDS YY 00 B0 RB0 Y Y 0 DS1557 FUNCTION/RANGE YEAR MONTH DATE DAY HOUR MINUTES SECONDS CONTROL WATCHDOG INTERRUPTS ALARM DATE ALARM HOURS ALARM MINUTES ALARM SECONDS UNUSED FLAGS 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-39 01-31 00-23 00-59 00-59 X = Unused, read/writable under Write and Read bit control FT = Frequency Test bit OSC = Oscillator start/stop bit W = Write bit R = Read bit WDS = Watchdog Steering bit BMB0-BMB4 = Watchdog Multiplier bits RB0-RB1 = Watchdog Resolution bits AE = Alarm Flag Enable Y = Unused, read/writable without Write and Read bit control ABE = Alarm in battery Back-up mode enable AM1-AM4 = Alarm Mask bits WF = Watchdog Flag AF = Alarm Flag 0 = 0 and are read only BLF = Battery Low Flag CLOCK OSCILLATOR CONTROL The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the oscillator. The DS1557 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC bit set to a 1. READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC Registers. This puts the external registers into a static state allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is set to a 0. 5 of 19 5 Page DS1557 READ CYCLE, AC CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ±10%) 70 ns access 100 ns access PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Read Cycle Time tRC 70 100 ns Address Access Time tAA 70 100 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 70 100 ns CE Data Off time tCEZ 25 35 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 35 55 ns OE Data Off Time tOEZ 25 35 ns Output Hold from Address tOH 5 5 ns READ CYCLE, AC CHARACTERISTICS (0°C to 70°C; VCC = 3.3V ±10%) 120 ns access 150 ns access PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Read Cycle Time tRC 120 150 ns Address Access Time tAA 120 150 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 120 150 ns CE Data Off time tCEZ 40 50 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 100 130 ns OE Data Off Time tOEZ 35 35 ns Output Hold from Address tOH 5 5 ns 11 of 19 11 Page

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