PDF 54SXxx Data sheet ( Hoja de datos )

Número de pieza	54SXxx
Descripción	General Purpose SDRAM Controller
Fabricantes	Actel
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No Preview Available ! v2.0 General-Purpose SDRAM Controller SDRAM Controller Functional Description The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly incrementing the address. The user starts a burst at a specified address and the burst continues until the user terminates it. SDRAM Controller Signals The SDRAM controller communicates with a user’s functions and drives the control signals into the SDRAM. When the controller recognizes the start of a write cycle, the controller prepares the SDRAM to accept data and then indicates readiness by driving the WR_BE_RDY signal. When the controller recognizes the start of a read cycle, the controller prepares the SDRAM to provide data and then indicates readiness by driving the RD_BE_RDY signal. The WR_BE_RDY and RD_BE_RDY signals are one-stage pipelined. On write cycles, the WR_BE_RDY signal is asserted one clock cycle prior to the time when data can actually be accepted by the SDRAM. On read cycles, the RD_BE_RDY signal is asserted one clock cycle prior to the time when SDRAM data is valid. In general, the *_RDY signals indicate that the SDRAM and controller will ready for data transfer on the next cycle. CLK RESET_N ACTIVATE WR_CYC ADDR CYC_DONE WR_BE_DONE RD_BE_DONE RD_BE_RDY WR_BE_RDY MADDR CSn RASn CASn WEn BA DQM CKE Figure 1 • SDRAM Controller The user provides a WR_BE_NOW and RD_BE_NOW signal to the controller. When WR_BE_RDY and WR_BE_NOW are both asserted at the same time, or when RD_BE_RDY and RD_BE_NOW are both asserted at the same time, data is transferred. If the WR_BE_NOW signal is not asserted, the controller will retain its current address until the WR_BE_NOW signal asserts at which time data is transferred. Because of the pipelined nature of the SDRAM and the assumption that burst addresses are incremented linearly, a deassertion of RD_BE_NOW causes delay while the controller backs up and refills the pipeline. At the conclusion of a cycle, the user asserts the CYCLE_DONE signal for one cycle. Table 1 • SDRAM Controller Signals Name Description Inputs from the User’s System Clk This is the system clock. The controller can transfer data at this rate during bursts. RESETn This is a reset signal. Assertion of this signal causes the SDRAM to be initialized. ACTIVATE A pulse on this signal causes the Controller to prepare the SDRAM for a cycle. WR_CYC This signal defines the type of cycle started when the ACTIVE (ACTIVATE?) signal is asserted. ADDR(M:0) This is the beginning address of the burst. CYC_DONE This signal causes the cycle to be terminated. WR_BE_NOW This signal indicates that the user wants the currently valid data to be written. RD_BE_NOW This signal indicates that the user will accept the data on this cycle. Outputs to the User’s System February 2000 © 2000 Actel Corporation 1 1 page Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44-(0)125-630-5600 Fax: +44-(0)125-635-5420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81-(0)3-3445-7671 Fax: +81-(0)3-3445-7668 5172153-0/2.00 5 Page

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