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PDF XPC862 Data sheet ( Hoja de datos )
| Número de pieza | XPC862 | |
| Descripción | XPC862 | |
| Fabricantes | Motorola Semiconductors | |
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Hardware Specification
MPC862 EC/D
Rev. 0.3, 04/2002
MPC862 Family
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC862 family (refer to Table 1 for a list
of devices). The MPC862P is the superset device of the MPC862 family. This document
contains the following topics:
Topic
Page
Part I, “Overview”
Part II, “Features”
Part III, “Maximum Tolerated Ratings”
Part IV, “Thermal Characteristics”
Part V, “Power Dissipation”
Part VI, “DC Characteristics”
Part VII, “Thermal Calculation and Measurement”
Part VIII, “Layout Practices”
Part IX, “Bus Signal Timing”
Part X, “IEEE 1149.1 Electrical Specifications”
Part XI, “CPM Electrical Characteristics”
Part XII, “UTOPIA AC Electrical Specifications”
Part XIII, “FEC Electrical Characteristics”
Part XIV, “Mechanical Data and Ordering Information”
Part XV, “Document Revision History
1
2
6
7
8
8
9
12
13
41
43
66
69
73
87
Part I Overview
The MPC862 is a derivative of Motorola’s MC68360 Quad Integrated Communications
Controller (QUICC™) and part of the PowerQUICC™ family of devices. It is a versatile
single-chip integrated microprocessor and peripheral combination that can be used in a variety
mof controller applications and communications and networking systems. The MPC862
oprovides enhanced ATM functionality over that of other ATM-enabled members of the
.cMPC860 family.
t4uThe CPU on the MPC862 is a 32-bit MPC8xx core that incorporates memory management
e units (MMUs) and instruction and data caches. The communications processor module (CPM)
e from the MC68360 QUICC has been enhanced by the addition of the inter-integrated
h controller (I2C) channel. The memory controller has been enhanced, enabling the MPC862 to
www.datas PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1 page  
Features
— Supports master and slave modes
— Supports multiple-master operation on the same bus
• One inter-integrated circuit (I2C) port
— Supports master and slave modes
— Multiple-master environment support
• Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, clocking
— Allows dynamic changes
— Can be internally connected to six serial channels (four SCCs and two SMCs)
• Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC862 or MC68360
• PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— 8 memory or I/O windows supported
• Low power support
— Full on—All units fully powered
— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
— Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for
fast wake up
— Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer.
— Power down mode— All units powered down except PLL, RTC, PIT, time base and
decrementer
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally
• 3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK
• 357-pin ball grid array (BGA) package
The MPC862 is comprised of three modules that each use the 32-bit internal bus—the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). The MPC862P block
diagram is shown in Figure 1.
MOTOROLA
MPC862 Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
5 Page 
Thermal Calculation and MeasurementEstimation Using Simulation
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80
Board Temperture Rise Above Ambient Divided by Package
Power
Figure 2. Effect of Board Temperature Rise on Thermal Behavior
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
TJ = TB +( RθJB x PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temperature ºC
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT +( ΨJT x PD)
where:
MOTOROLA
MPC862 Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XPC862.PDF ] | |
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