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PDF L64734 Data sheet ( Hoja de datos )
| Número de pieza | L64734 | |
| Descripción | (L64733) Tuner and Satellite Receiver Chipset | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
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L64733/L64734
Tuner and Satellite
Receiver Chipset
Datasheet
The L64733/34 chipset is designed specifically to meet the needs of
satellite broadcast digital TV and is compliant with the European digital
video broadcast (DVB-S) standard and the technical specifications for
DSS systems. The chipset forms a complete “L-Band to bits” system.
A typical application of the L64733/34 chipset is satellite digital TV
reception in accordance with ETS 300 421. Figure 1 shows the
L64733/34 chipset satellite receiver implemented in a typical satellite
receiver set-top decoder box.
Figure 1 Block Diagram of Set-Top Decoder Box Using the L64733/34 Chipset
Optional
DRAM
256K x 16
Optional
Decryption
Engine
Satellite In
RF Out
(Loop Through)
L64733/L64734 Chipset
L64733
L64734
/ 16
/8
CO
[7:0]
Transport
Demux
8/
High-Speed
Port
Microprocessor
Data and
Address Bus
Microprocessor
NTSC
PAL
S-Video
L-Speaker
R-Speaker
PAL / NTSC
Encoder
PCM
Audio DAC
/2
27 MHz
CCIR601VIDEO
/
8
PCM AUDIO
/3
VCXO
/ 8 Audio
Oversampling
Clock
Audio/Video Audio/Video PES
Decoder
64/32
SDRAM
256K x 64
256K x 32
The L64733/34 chipset consists of the L64734 Satellite Receiver IC, the
L64733 Tuner IC, and an on-chip synthesizer. Figure 2 shows a simplified
block diagram of this chipset.
August 2000
Copyright © 1999, 2000 by LSI Logic Corporation. All rights reserved.
1
1 page  
range from 925–2175 MHz, with a 0.5 MHz step size when using a
4-MHz crystal reference. The on-chip VCO tuning frequency is 543 MHz
to 1088 MHz. To tune channels from 925–1086 MHz, the L64734
disables the frequency doubler (X2 block) on the L64733. To tune
channels from 1086 MHz to 2175 MHz, the L64734 enables the
frequency doubler. The VCO requires an external resonant tank circuit,
which includes varactor diodes to vary the frequency of oscillation.
The VCO signal goes to the Prescaler block before it is passed to the
L64734 differentially through the PSOUTp and PSOUTn pins. The
L64734 MODp and MODn differential signals control the divider ratio for
the Prescaler block. The L64734 dynamically changes the divide ratio to
ensure that the tuning step size is not affected by the divider. The
L64734 contains programmable counters to further divide the signal in
frequency before the signal is fed back to the L64733 through the PLLINp
and PLLINn pins. The crystal reference oscillator frequency is divided by
eight, then fed to the phase detector. The phase detector generates a
current signal proportional to the difference in phase between PLLINp,
PLLINn, and the divided crystal frequency. A charge pump circuit (which
controls pins CP, FB) and an external transistor (to buffer the L64733
against the tuning voltage of 28 V) generate the current. The current is
filtered, fed through a discrete loop filter, and converted to a tuning
voltage that drives the external varactor diodes for the VCO tank circuit.
A complete frequency controlled loop is formed, and the VCO frequency
can be varied by changing the frequency divider ratios in the L64734
registers. See Figure 7 on page 22 for more details regarding the
external circuitry for the VCO, crystal oscillator, charge pump, tank
circuitry, and entire frequency-controlled loop.
The chipset provides maximum integration and flexibility for system
designers at a minimum cost. The number of external components
required to build a system is minimal because the synthesizer, variable
rate filters, and clock and carrier loops are all integrated into the two
devices.
L64733/L64734 Tuner and Satellite Receiver Chipset
5
5 Page 
INSEL
RF Port Input Select
Input
When the INSEL signal is asserted, the L64733 is in
normal mode. When the INSEL signal is deasserted, the
L64733 is in Loop-Through mode. In this mode, the RFIN
signal is looped through to the RFOUT signal, and the
L64733 local oscillator is shut off.
MODn, MODp Prescaler Modulus
Input
The MOD differential signals form a PECL input that sets
the prescaler modulus. When the MODp signal is positive
with respect to the MODn signal, the prescaler modulus
is set to 32 (divide by 32). When the MODn signal is
positive with respect to the MODp signal, the prescaler
modulus is set to 33 (divide by 33).
PLLINn, PLLINp
Phase Detector
Input
The PLLIN differential signals form the phase detector
input and are connected to the L64734 PLLINp and
PLLINn output signals. See the L64734 PLLINp and
PLLINn descriptions in the subsection entitled
“Synthesizer Control Interface” on page 19.
QDCn, QDCp Q-Channel DC Offset Correction
Input
Connect a 0.1 µF (or larger) capacitor between the QDCp
and QDCn signals.
Channel Data Signals
This section describes the channel data signals from the L64733 to the
L64734.
IOUTn, IOUTp I-Channel Baseband Data
Output
The IOUT differential signals form the in-phase data
provided to the L64734.
QOUTn, QOUTp
Q-Channel Baseband Data
Output
The QOUT differential signals form the quadrature-phase
data provided to the L64734.
L64733/L64734 Tuner and Satellite Receiver Chipset
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L64734.PDF ] | |
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